Publications

PEER-REVIEWED JOURNAL PAPERS

  • Alok Kamal, Jawar Singh, "Simulation based Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks," IEEE Transactions on Electron Devices, 67 (6), 2020.

  • Md. Hasan Raza Ansari, and Jawar Singh, \Capacitorless 2T-DRAM for Higher Retention Time and Sense Margin", IEEE Transactions on Electron Devices, vol.pp, 2020 (IF 2.74).

  • Neha Kamal, Avinash Lahgere, and Jawar Singh, \Evaluation of Radiation Resiliency on Emerging Junctionless/Dopingless Devices and Circuits", IEEE Transactions on Device and Materials Reliability, vol. Early Access, no.2 , Nov. 2019.

  • Ankit Sirohi, Chitrakant Sahu, and Jawar Singh, \Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications", IEEE Access, vol.7, pp 141810 - 141816, August 2019 (IF 4.01).

  • Deepti Gola, Balraj Singh, Jawar Singh and Pramod Tiwari, \Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor with Substrate Bias Induced E ects", IEEE Transactions on Electron Devices, vol.67, no.7, pp 2876 - 2883, May 2019 (IF 2.74).

  • Neha Kamal, Meena Panchore, and Jawar Singh, \3-D Simulation of Junction- and Dopingfree Field-e ect Transistor under Heavy Ion Irradiation", IEEE Transactions on Device and Materials Reliability, vol. 18, pp 173-179, no.2 , March 2018.

  • Lokesh Kumar Bramhane, and Jawar Singh, \Improved performance of bipolar charge plasma transistor by reducing the horizontal electric field", Superlattices and Microstructures (Elsevier),Vol 104, April 2017, (IF 2.13).

  • Muhammad Khalid, Jawar Singh and Saraju P. Mohanty, \Impact of Channel Hot Carrier Effect in Junction- and Doping-Free Devices and Circuits", Journal of Nanoelectronics and Optoelectronics, vol.12, no.1, Jan 2017.

  • Meena Panchore, Jawar Singh and Saraju P. Mohanty, \Impact of Channel Hot Carrier Effect in Junction- and Doping-Free Devices and Circuits", IEEE Transactions on Electron Devices, vol.63, no.12, Oct 2016 (IF 2.74).

  • Kanchan Cecil, and Jawar Singh, \Influence of Germanium source on dopingless tunnel-FET for improved analog/RF performance", Superlattices and Microstructures (Elsevier), Vol 96, November 2016 (IF 2.13).

  • Abhishek Sahu, Lokesh Kumar Bramhane and Jawar Singh, \Symmetric Lateral Doping-free BJT: A Novel Design for Mixed Signal Applications", IEEE Transactions on Electron Devices, vol.67, no.7, May 2016 (IF 2.60).

  • Lokesh Kumar Bramhane, and Jawar Singh, \Two-zone SiGe base heterojunction bipolar charge plasma transistor for next generation analog and RF applications", Superlattices and Microstructures (Elsevier), Vol 96, November 2016 (IF 2.13).

  • Avinash Lahgere, Meena Panchore, and Jawar Singh, \Dopingless Ferroelectric Tunnel FET Architecture for the Improvement of Performance of Dopingless n-Channel Tunnel FETs", Superlattices and Microstructures (Elsevier), Vol 96, August 2016 (IF 2.13).

  • Muhammad Khalid and Jawar Singh, \Memristor based unbalanced ternary logic gates", Analog Integrated Circuits and Signal Processing (Springer), Vol 87 (3), pp 339-406, 2016.

  • Vishwas Shrivastava, Anup Kumar, Chitrakant Sahu and Jawar Singh, \Temperature sensitivity analysis of dopingless charge-plasma transistor", Solid-State Electronics (Elsevier), November 2015, ISSN 0038-1101 (IF 1.50).

  • Deep Kishore Parsediya, Jawar Singh and Pavan Kumar Kankar, \Variable width based stepped MEMS cantilevers for micro or pico level biosensing and e ective switching", Journal of Mechanical Science and Technology (Springer), Vol 29, n0. 11, pp 4823-4832, Nov 2015, 1976-3824 (IF 0.84).

  • Chitrakant Sahu and Jawar Singh, \Scalability and Process Induced Variation Analysis of Polarity Controlled Silicon Nanowire Transistor", Journal of Computational Electronics (Springer), August 2015 (IF 1.52).

  • Avinash Lahgere, Chitrakant Sahu and Jawar Singh, \PVT Aware Design of Dopingless Dynamically Con gurable Tunnel-FET", IEEE Transactions on Electron Devices, vol.62, no.8, August 2015 (IF 2.60).

  • Chitrakant Sahu and Jawar Singh, \Potential Bene ts and Sensitivity Analysis of doping-less Transistor for Low Power Applications", IEEE Transactions on Electron Devices, vol.62, no.3, pp.729,735, March 2015 (IF 2.60).

  • Sunil Pandey and Jawar Singh, \A low power and high gain CMOS LNA for UWB applications in 90nm CMOS process", Microelectronics Journal (Elsevier), Volume 46, Issue 5, May 2015, Pages 390-397 (IF 0.91).

  • Avinash Lahgere, Chitrakant Sahu and Jawar Singh, \An Electrically Doped Dynamically Configurable Field Effect Transistor for Low Power and High Performance Applications", Electronics Letters, IET-UK (August 2015) (IF 1.15).

  • LK Bramhane, N Upadhyay, JR Veluru and Jawar Singh, \Symmetric bipolar charge-plasma transistor with extruded base for enhanced performance", Electronics Letters, IET-UK (June 2015) (IF 1.15).

  • Sunil Pandey and Jawar Singh, \A 0.6V low-power and high-gain ultra-wideband low-noise amplifier with forward-body-bias technique for low-voltage operations", IET-UK Microwaves, Antennas & Propagation, Volume 9, Issue 8, pp 728 - 734 2015, (IF 0.91).

  • Chitrakant Sahu and Jawar Singh, \Charge-Plasma Based Process Variation Immune Junctionless Transistor", Electron Device Letters, IEEE, Volume 35, Issue 3, pp 411 - 413, 2014/3 (IF 3.05).

  • Chitrakant Sahu, Ajanta Ganguly and Jawar Singh, \Design and Performance Projection of Symmetric Bipolar Charge-plasma Transistor on SOI", IET-UK, Electronics Letters, IET-UK (Sept. 2014) (IF 1.15).

  • Anup Shrivastava, Komal Singh and Jawar Singh, \Improved Dual Sided Doped Memristor: Modeling and Applications", IET-UK, Journal of Engineering (April 2014).

  • Deep Kishore Parsediya, Jawar Singh and Pavan Kumar Kankar, \Simulation and Analysis of Highly Sensitive MEMS Cantilever Designs for \in vivo Label Free" Biosensing", Elsevier, Vol 14, Journal Procedia Technology, 2014/12/31.

  • Chitrakant Sahu and Jawar Singh, \Device and Circuit Performance Analysis of Double Gate Junctionless Transistors at Lg=18nm", IET-UK, Journal of Engineering (Feb 2014).

  • Chitrakant Sahu, Pragya Swami, S Sharma and Jawar Singh, \Simpli ed Drain Current Model for Pinch-o Double Gate Junctionless Transistor", IET-UK, Electronics Letters, IET-UK , Jan 2014, V 50/2 (IF 1.15).

  • Jawar Singh and N. Vijaykrishnan, \A highly reliable NBTI Resilient 6T SRAM cell", Microelectronics Reliability (Elsevier), Volume 53, Issue 4, April 2013, Pages 565-572, ISSN 0026-2714 (IF 1.28).

  • Saraju P. Mohanty, Jawar Singh, Elias Kougianos, and Dhiraj K. Pradhan, \Statistical DOE-ILP Based Power-Performance-Process P3) Optimization of Nano-CMOS SRAM", Integration, the VLSI Journal (Elsevier), Volume 45, Issue 1, January 2012, Pages 33{45, ISSN 0167-9260 (IF 0.72).

  • Jawar Singh, Dhiraj K. Pradhan, Simon Hollis and Saraju P. Mohanty, \A single ended 6T SRAM cell design for ultra-low-voltage applications", Journal of Institute of Electronics, Information and Communication Engineers (IEICE), Japan, Vol. 5 (2008), No. 18 pp. 750-755.

  • Jawar Singh and R.S Anand, \Computer aided analysis of phonocardiogram", Journal of Medical Engineering & Technology, 2007, Vol. 31, No. 5 , Pages 319-323.

ARXIV PAPERS

  • In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML Applications A Kumar, J Singh, SM Beeraka, B Gupta, ArXiv, arXiv:2005.09526, 2020.

  • Alok Kumar Kamal and Jawar Singh, “Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks”, arXiv preprint arXiv:1909.00669, 2019/09/02.

  • Kanchan Cecil and Jawar Singh, “Electrostatically Doped Heterojunction TFET with Enhanced Driving Capabilities for Low Power Applications”, arXiv preprint arXiv:1512.06232, 2015/12/19.

  • Chitrakant Sahu, Avinash Lahgere and Jawar Singh, “A Dynamically Configurable Silicon Nanowire Field Effect Transistor based on Electrically Doped Source/Drain”, arXiv:1412.4975, 12/2014, pp 2.

CONFERENCE PAPERS

  • Sandeepkumar Pandey, Jawar Singh, and Pramod K. Tiwari , “Energy and Area Aware Digital Fingerprint Generator Using Intrinsic Randomness”, 25th IEEE international conference on noise and fluctuations, June 2019, Neuchˆatel (Switzerland).

  • Deb Deep, Jimson Mathew, and Jawar Singh, “and Pramod K. Tiwari”, 7th International Conference on Smart Computing & Communications, June 2019, Malaysia.

  • Nawaz Shafi, Chitrakant Sahu, C Periasamy, and Jawar Singh, “SiGe Source Charge Plasma TFET for Biosensing Applications”, 2017 IEEE International Symposium on Nanoelectronic and Information Systems, pp 93-98, 18/12/2017, Bhopal, INDIA.

  • Venkata P Yanambaka, Saraju P Mohanty, Elias Kougianos, Prabha Sundaravadivel and Jawar Singh, “Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET”, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 665-670, 3/7/2017, Bochum, Germany.

  • Venkata P Yanambaka, Saraju P Mohanty, Elias Kougianos, Prabha Sundaravadivel and Jawar Singh, “Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function”, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 609-614, 3/7/2017, Bochum, Germany.

  • Venkata P Yanambaka, Saraju P Mohanty, Elias Kougianos and Jawar Singh, “Secure Multikey Generation Using Ring Oscillator Based Physical Unclonable Function”, 2016 IEEE International Symposium on Nanoelectronic and Information Systems, pp 200-205, 19/12/2016, Gwalior, INDIA.

  • Meena Panchore, Jawar Singh, Saraju P Mohanty, and Elias Kougianos , “Compact Behavioral Modeling and Time Dependent Performance Degradation Analysis of Junction and Doping Free Transistors”, 2016 IEEE International Symposium on Nanoelectronic and Information Systems, pp 194-199, 19/12/2016, Gwalior, INDIA.

  • Chaitanya Maradana and Jawar Singh, “Proposal of Heterogate Technique for Performance Enhancement of DM-TFET”, 2016 IEEE International Symposium on Nanoelectronic and Information Systems, pp 118-123,19/12/2016, Gwalior, INDIA.

  • Muhammad Khalid and Jawar Singh, “Memristor Crossbar-Based Pattern Recognition Circuit Using Perceptron Learning Rule”, 2016 IEEE International Symposium on Nanoelectronic and Information Systems, pp 236-239, 19/12/2016, Gwalior, INDIA.

  • Kanchan Cecil and Jawar Singh, “Performance Enhancement of Dopingless Tunnel-FET Based on Ge-Source with High-k”, 2015 IEEE International Symposium on Nanoelectronic and Information Systems, pp 19-22, Indore, INDIA.

  • Lokesh Kumar Bramhane and Jawar Singh, “Extended Base Schottky-Collector Bipolar Charge Plasma Transistor”, 2015 IEEE International Symposium on Nanoelectronic and Information Systems, pp 137-140, Indore, INDIA.

  • Saurabh Bhaskar and Jawar Singh, “Process variation immune dopingless dynamically reconfigurable FET”, Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on, pp 257-260, Singapore.

  • Anup Kumar, Chitrakant Sahu and Jawar Singh, “Subthreshold Analog/RF performance estimation of doping-less DGFET for ULP applications”, Emerging Electronics (ICEE), 2014 IEEE 2nd International Conference on, pp 1-4, IISC Bangalore, INDIA, 2014/12/3.

  • Rajesh Singh Lodhi, Som Dutt Pandey, Chitrakant Sahu and Jawar Singh, “Performance comparison of bulk and SOI planar junctionless SONOS memory”, Emerging Electronics (ICEE), 2014 IEEE 2nd International Conference on, pp 1-4, IISC Bangalore, INDIA, 2014/12/3.

  • Deep Kishore Parsediya Jawar Singh and Pavan Kumar Kankar, “Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimization”, 2014 VLSI Design and Test, 18th International Symposium on (VDAT), INDIA, 2014/7/16.

  • Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh and Manoj S Parihar, “Realization of efficient RF energy harvesting circuits employing different matching technique”, 2014 IEEE Fifteenth International Symposium on Quality Electronic Design (ISQED), pp 754-761 CA, USA, 2014/3/3.

  • Anup Shrivastava and Jawar Singh, “Dual-sided doped memristor and it’s SPICE modelling for improved electrical properties”, 2014 IEEE Fifteenth International Symposium on Quality Electronic Design (ISQED), pp 317-322, CA, USA, 2014/3/3.

  • Komal Singh, Chitrakant Sahu and Jawar Singh, “Linearly separable pattern classification using memristive crossbar circuits”, 2014 IEEE Fifteenth International Symposium on Quality Electronic Design (ISQED), pp 323-329, CA, USA, 2014/3/3.

  • Anup Shrivastava and Jawar Singh, “Dual sided doped memristor and it’s mathematical modelling”, Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on, pp 49-51, Abu Dhabi, 2013/12/8.

  • Pankaj Kumar, Chitrakant Sahu, Anup Shrivastava, Jawar Singh, and P.N. Kondekar, “Characteristics of gate inside junctionless transistor with channel length and doping concentration”, Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of, pp 1-2, Hong Kong, 2013/6/3.

  • Chitrakant Sahu, Jawar Singh, and P.N. Kondekar, “Investigation of ultra-thin BOX junctionless transistor at channel length of 20 nm”, Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of, pp 1-2, Hong Kong, 2013/6/3.

  • Sachin Agrawal, Sunil Pandey, Jawar Singh, and P.N. Kondekar, “An Efficient RF Energy Harvester with Tuned Matching Circuit”, 2013 VLSI Design and Test, pp 138-145, INDIA, 2013/1/1.

  • GK Reddy, Kapil Jainwal, Jawar Singh, and Saraju P Mohanty, “Process variation tolerant 9T SRAM bitcell design”, 2012 IEEE Thirteenth International Symposium on Quality Electronic Design (ISQED), pp 493-497, CA, USA, 2012/3/19.

  • Jawar Singh, Dilip S Aswar, Saraju P Mohanty, Dhiraj K Pradhan, “A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead”, 2010 IEEE Eleventh International Symposium on Quality Electronic Design (ISQED), pp 131-138, CA, USA, 2010/3/22.

  • A Ricketts, Jawar Singh, K Ramakrishnan, N Vijaykrishnan, D K Pradhan, “Investigating the impact of NBTI on different power saving cache strategies”, 2010 ACM-IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 592-597, Germany, 2010/3/8.

  • Jawar Singh, Krishnan Ramakrishnan, S Mookerjea, Suman Datta, Narayanan Vijaykrishnan, D Pradhan, “A novel si-tunnel FET based SRAM design for ultra low-power 0.3 VV DD applications”, 2010 ACM-IEEE Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pp 181-186, 2010/1/18.

  • S Mookerjea, D Mohata, R Krishnan, Jawar Singh, A Vallett, A Ali, T Mayer, V Narayanan, D Schlom, A Liu, S Datta, “Experimental demonstration of 100nm channel length In 0.53 Ga 0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications”, 2009 IEEE International Electron Devices Meeting (IEDM), pp 1-3, 2009/12/7.

  • Jawar Singh, Dhiraj K Pradhan, Simon Hollis, Saraju P Mohanty, J Mathew, “Single ended 6T SRAM with isolated read-port for low-power embedded systems”, 2009 ACM-IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 917-922, Germany, 2009/4/20.

  • Jawar Singh, Jimson Mathew, Saraju P Mohanty, Dhiraj K Pradhan, “Single ended static random access memory for low-vdd, high-speed embedded systems”, 2009 22nd International Conference on VLSI Design (VLSID), pp 307-312, INDIA, 2009/1/5.

  • Yi Xin Su, Jimson Mathew, Jawar Singh and Dhiraj K Pradhan, “Pseudo parallel architecture for AES with error correction”, 2008 21st IEEE International SOC Conference (SOCC), pp 187-190, CA, USA, 2008/9/17.

  • Jawar Singh Jimson Mathew, Dhiraj K Pradhan, Saraju P Mohanty, “Failure analysis for ultra low power nano-CMOS SRAM under process variations”, 2008 21st IEEE International SOC Conference (SOCC), pp 187-190, CA, USA, 2008/9/17.

  • Jawar Singh Jimson Mathew, Dhiraj K Pradhan, Saraju P Mohanty, “A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies”, 2008 21st IEEE International SOC Conference (SOCC), pp 243-246, CA, USA, 2008/9/17.

  • Jimson Mathew, Jawar Singh, Anas Abu Taleb Dhiraj K Pradhan, “Fault tolerant reversible finite field arithmetic circuits”, 2008 14th IEEE International On-Line Testing Symposium (IOLTS), pp 188-189, Rhodes, Greece, 2008/7/7.

  • Jawar Singh, Jimson Mathew, Dhiraj K Pradhan, Saraju P Mohanty, “A nano-CMOS process variation induced read failure tolerant SRAM cell”, 2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp 3334-3337,Seattle, USA, 2008/5/18.

  • Jimson Mathew,Jawar Singh, Abusaleh M Jabir, Mohammad Hosseinabady, Dhiraj K Pradhan, “Fault tolerant bit parallel finite field multipliers using LDPC codes”, 2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp 1684-1687,Seattle, USA, 2008/5/18.

  • Babita R Jose, P Mythili,Jawar Singh, Jimson Mathew, “A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards”, 2007 IEEE 10th International Conference on Information Technology,(ICIT 2007), pp 127-132,INDIA, 2007/12/17.

  • Jawar Singh, J Mathew, M Hosseinabady, DK Pradhan, “Single event upset detection and correction”, 2007 IEEE 10th International Conference on Information Technology,(ICIT 2007), pp 127-132,INDIA, 2007/12/17.

  • Jawar Singh, Jimson Mathew, Saraju P Mohanty, Dhiraj K Pradhan, “Statistical analysis of steady state leakage currents in nano-CMOS devices”, 2007 Norchip, 2007, pp 1-4, Denmark, 2007/11/19