Call for Benchmarks
We invite the community to contribute real-world workloads from any FPGA application domain as representative benchmarks. This effort is an attempt towards the development of community-driven benchmark suites for FPGA architecture and CAD for applications/domains that are not currently well represented in open-source benchmark suites.
Submission guidelines:
Must be open-source.
Full application workloads are preferred, though kernels or microbenchmarks are welcome when appropriate.
Any programming model is acceptable (RTL, HLS, or emerging languages). In case of HLS or emerging languages, the generated RTL must be submitted as well.
Must be verified and usable with open-source FPGA tools (Yosys, VTR, etc). We have made this easy for you. Please use this GitHub repo as a template. Fork it, follow the instructions in the README to test your design and then submit the link of your fork.
One submission can include multiple benchmarks.
Submissions should include:
Benchmark code provided as a GitHub link, including a README with setup and execution instructions.
A 2-page (excluding references) paper in ACM conference format, describing the benchmark, its relevance to the application domain, and methods employed for verification and open-source tool compatibility.
Selected benchmarks will be featured through poster flash talks and a poster session at the workshop.
Benchmarks and papers do not need to be new unpublished work.
Submission Link:
https://cmt3.research.microsoft.com/WDSFPGA2026
More guidelines below.
We are seeking early-stage, unconventional, and forward-looking ideas on domain-specialized FPGA architectures and CAD, to spark creative dialogue and inspire new directions for the field.
We welcome position or idea papers that explore speculative concepts, qualitative insights, or emerging research visions.
Submission guidelines:
Can be focused on architectures or CAD or applications for FPGAs.
Quantitative results are not required.
Submissions should:
Be 3-4 pages long (ACM conference format), excluding references.
Include an abstract and expected impact/motivation of the idea/position.
Selected submissions will be given an opportunity for a 10-15 min presentation followed by interactive discussion.
Papers on ideas and positions do not need to be new unpublished work.
Submission Link:
https://cmt3.research.microsoft.com/WDSFPGA2026
More guidelines below.
Author guidelines
Authors need to have a CMT account before submitting their work:
Here is a link to create the account: https://cmt3.research.microsoft.com/docs/help/general/account-creation.html
Here is a link for authors on how to submit a paper: https://cmt3.research.microsoft.com/docs/help/author/author-submission-form.html
Submission Template
Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template.
LaTeX users should use the format of the sample-sigconf.pdf file which can be found in the Samples folder of the zipped master file.
Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the template page.
Plagiarism Declaration
Submissions should be guaranteed by the authors to be their original work. They can be previously published, or currently accepted, or under consideration for acceptance at another venue.
Rebuttal Process
The workshop review process does not include a rebuttal phase for authors to provide a response to reviewers.
Author Participation
At least one of the authors of each accepted submission is required to present the work at the workshop. Accommodations will be made for authors who face documented visa issues due travel restrictions.
The Microsoft CMT service was used for managing the peer-reviewing process for this conference. This service was provided for free by Microsoft and they bore all expenses, including costs for Azure cloud services as well as for software development and support.