* denotes a corresponding author. + denotes a co-first author.
[Journal, TCAS-I] Jaehee Kim, Changhyeon Kim, Sangbu Yun, Dongyun Kam, Soonhyun Kwon, Yongjune Kim, and Youngjoo Lee*, "Hybrid ordered statistics decoding of short-length BCH codes for URLLC systems: Theoretical analysis and decoder implementation," Accepted to IEEE Transactions on Circuits and Systems I: Regular Papers. (Invited)
[Conference, ISICAS] Jaehee Kim, Changhyeon Kim, Sangbu Yun, Dongyun Kam, Soonhyun Kwon, Yongjune Kim, and Youngjoo Lee*, "Hybrid ordered statistics decoding of short-length BCH codes for URLLC systems: Theoretical analysis and decoder implementation," IEEE International Symposium on Integrated Circuits and Systems (ISICAS, TCAS-I Special Issue), Qingdao, China, Oct. 2025.
[Conference, APCCAS] Seungwoo Hong, Jung Gyu Min, Jin Hyun, Jaehee Kim, Dongyun Kam, Eunji Yoo, Pilsu Kim, Jaehyung Yoo, Hyoung-Euk Lee, and Youngjoo Lee*, "FPGA-based real-time ISP accelerator using low-cost line buffers and non-linear functions," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Busan, Korea, Oct. 2025.
[Conference, APCCAS] Junehyuk Oh, Soonhyun Kwon, Dongyun Kam, and Youngjoo Lee*, "On the hardware efficiency of short-length polarization-adjusted convolutional polar decoders," IEEE Asia Pacific Conference of Circuits and Systems (APCCAS), Busan, Korea, Oct. 2025.
[Journal, JBHI] Sunwoo Yoo, Seungwoo Hong, Dongyun Kam, and Youngjoo Lee*, "A lightweight ML-based ECG classification system using self-personalized anomaly detector," IEEE Journal of Biomedical and Health Informatics, vol. 29, no. 10, pp. 7274-7284, Oct. 2025.
[Conference, HPCA] Dongyun Kam, Myeongji Yun, Sunwoo Yoo, Seungwoo Hong, Zhengya Zhang, and Youngjoo Lee*, "Panacea: Novel DNN accelerator using accuracy-preserving asymmetric quantization and energy-saving bit-slice sparsity," IEEE International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, NV, USA, Mar. 2025. (Samsung HumanTech Bronze Award)
[Journal, TCAS-I] Jaehee Kim+, Sangil Han+, Dongyun Kam, Byeong Yong Kong, and Youngjoo Lee*, "A design framework for cost-efficient sorters with arbitrary input/output constraints," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 12, pp. 5410-5419, Dec. 2024. (Invited)
[Journal, TCAS-II] Dain Park, Dongyun Kam, Sangbu Yun, Jeongwon Choe, and Youngjoo Lee*, "Hard-decision SCL polar decoder with weighted pruning operation for storage applications," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 9, pp. 4181-4185, Sep. 2024.
[Conference, ISCAS] Sangil Han+, Jaehee Kim+, Dongyun Kam, Byeong Yong Kong, Mijung Kim, Young-Seok Kim, and Youngjoo Lee*, "Constrained sorter design using zero-one principle," IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, May 2024.
[Conference, ISSCC] Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, and Youngjoo Lee*, "A 21.9 ns, 15.7 Gbps/mm^2 (128, 15) BOSS FEC decoder for 5G/6G URLLC applications," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 2024.
[Conference, ISLPED] Jung Gyu Min, Dongyun Kam, Younghoon Byun, Gunho Park, and Youngjoo Lee*, "Energy-efficient RISC-V-based vector processor for cache-aware structurally-pruned transformers," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Vienna, Austria, Aug. 2023.
[Journal, TCAS-I] Dongyun Kam, Byeong Yong Kong, and Youngjoo Lee*, "Low-latency SCL polar decoder architecture using overlapped pruning operations," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 3, pp. 1417-1427, Mar. 2023.
[Conference, HPCA] Ranggi Hwang, Minhoo Kang, Jiwon Lee, Dongyun Kam, Youngjoo Lee, and Minsoo Rhu*, "GROW: A row-stational sparse-dense GEMM accelerator for memory-efficient graph convolutional neural networks," IEEE International Symposium on High-Performance Computer Architecture (HPCA), Montreal, QC, Canada, Feb. 2023.
[Journal, CL] Changhyeon Kim, Dongyun Kam, Seokki Kim, Giyoon Park, and Youngjoo Lee*, "Simplified ordered statistic decoding for short-length linear block codes," IEEE Communications Letters, vol. 26, no. 8, pp. 1720-1724, Aug. 2022.
[Conference, S.VLSI] Dongyun Kam, Byeong Yong Kong, and Youngjoo Lee*, "A 1.1µs 1.56Gb/s/mm^2 cost-efficient large-list SCL polar decoder using fully-reusable LLR buffers in 28nm CMOS technology," IEEE Symposium on VLSI Technology and Circuits (VLSI), Honolulu, HI, USA, June 2022.
[Journal, TCAS-I] Seungwoo Hong, Dongyun Kam, Sangbu Yun, Jeongwon Choe, Namyoon Lee, and Youngjoo Lee*, "Low-complexity and low-latency SVC decoding architecture using modified MAP-SP algorithm," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 4, pp. 1774-1787, Apr. 2022.
[Conference, DATE] Dongyun Kam+, Jung Gyu Min+, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, and Youngjoo Lee*, "Design and evaluation frameworks for advanced RISC-based ternary processor," IEEE/ACM Design, Automation and Test in Europe (DATE), Antwerp, Belgium, Mar. 2022.
[Conference, ASSCC] Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, and Youngjoo Lee*, "FPGA-based ordered statistic decoding architecture for B5G/6G URLLC IIOT networks," IEEE Asian Solid-State Circuits Conference (A-SSCC), Busan, Korea, Nov. 2021.
[Conference, ICASSP] Dongyun Kam, Byeong Yong Kong, and Youngjoo Lee*, "Low-latency polar decoder using overlapped SCL processing," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Toronto, Canada, Jun. 2021, pp. 4860-4864.
[Journal, TVLSI] Dongyun Kam, Hoyoung Yoo, and Youngjoo Lee*, "Ultralow-latency successive cancellation polar decoding architecture using tree-level parallelism," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 6, pp. 1083-1094, June 2021.
[Conference, ISCAS] Sangbu Yun, Dongyun Kam, Jeongwon Choe, Byeong Yong Kong, and Youngjoo Lee*, "Ultra-low-latency LDPC decoding architecture using reweighted offset min-sum algorithm," IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, Oct. 2020, pp. 1-5.
[Journal, Electronics] Seokha Hwang, Seungsik Moon, Dongyun Kam, Inn-Yeol Oh, and Youngjoo Lee*, "High-throughput and low-latency digital baseband architecture for energy-efficient wireless VR systems," MDPI Electronics, vol. 8, no. 7:815, pp. 1-13, July 2019.
[Journal, IEEE Access] Seungsik Moon, In-Soo Kim, Dongyun Kam, Dong-Woo Jee, Junil Choi*, and Youngjoo Lee*, "Massive MIMO systems with low-resolution ADCs: Baseband energy consumption vs. Symbol detection performance," IEEE Access, vol. 7, no. 1, pp. 6650-6660, Jan. 2019. (Samsung HumanTech Encouragement Paper Award)
[Conference, ISCAS] Dongyun Kam and Youngjoo Lee*, "Ultra-low-latency parallel SC polar decoding architecture for 5G wireless communications," IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019, pp. 1-5. (Student Travel Grant Award)