Publications:
Publications in Refereed Journals
1. B. Jena, S. Dash, G.P Mishra, “Improved switching speed of a CMOS inverter using work-function modulation engineering", IEEE TRANSACTION ON ELECTRON DEVICES (IEEE), Vol. 65, Pages 2422-2425.
2. B. Jena, S. Dash, G.P Mishra, “Impact of metal grain work function variability on ferroelectric insulation based GAA MOSFET”, IET Micro Nano Letter, Vol 13.
3. B. Jena, S. Dash, G.P Mishra, “Effect of underlap length variation on DC/RF performance of dual material cylindrical MOS", INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS (WILEY), Volume30, Issue2, Pages e2175.
4. B. Jena, S. Dash, G.P Mishra, “Electrostatic performance improvement of dual material cylindrical gate MOSFET using work-function modulation technique", SUPERLATTICES AND MICROSTRUCTURES (ELSEVIER), Volume97, Pages 212-220.
5. B.S Ramakrishna, B. Jena, S. Dash, G.P Mishra, “Investigation of electrostatic performance for a conical surrounding gate MOSFET with linearly modulated work-function", SUPERLATTICES AND MICROSTRUCTURE (ELSEVIER), Volume101, Pages 152-159.
6. B. Jena, S. Dash, K.P Pradhan, S.K Mohapatra, P.K Sahu, G.P Mishra, “Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime", ADVANCES IN NATURAL SCIENCES: NANOSCIENCE AND NANOTECHNOLOGY (IOP PUBLISHING), Volume6, Pages 035010.
7. B. Jena, B.S Ramakrishna, S. Dash, G.P Mishra, “Conical surrounding gate MOSFET: a possibility in gate-allaround family," ADVANCES IN NATURAL SCIENCES: NANOSCIENCE AND NANOTECHNOLOGY (IOP PUBLISHING), Volume7, Pages 015009.
8. S. Dash, B. Jena, A.S Lenka, G.P Mishra, “Impact of source pocket doping on RF and linearity performance of a cylindrical gate tunnel FET", INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICESANDFIELDS(WILEY),doi.org/10.1002/jnm.2283.
9. S. Dash, B. Jena, G.P Mishra, “A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping", SUPERLATTICES AND MICROSTRUCTURES (ELSEVIER), Volume101,Pages231-241.
10. B. Jena, S. Dash, K.P Pradhan, S.K Mohapatra, P.K Sahu, G.P Mishra “Investigation on cylindrical gate all around (GAA) to nano-wire MOSFET for circuit application", FACTA UNIVERSITATIS, SERIES: ELECTRONICS AND ENERGETICS, Volume28, Pages637-643.
11. B. Jena, S. Dash, G.P Mishra, “Inner-Gate-Engineered GAA MOSFET to Enhance the Electrostatic Integrity" NANO: Brief Reports and Reviews, Volume14, Pages 1950128-(1–8).
12. P. Keerthana, P. Praneeth Babu, T.Akhil Babu, B. Jena, “Performance Analysis of GAA MOSFET for Lower Technology Nodes”, JOURNAL OF ENGINEERING SCIENCE AND TECHNOLOGY REVIEW, Vol 13, Pages 39-43.
13. S Tayal, P Samrat, V Keerthi, B Jena, K Rajendra ,”Conventional vs. junctionless gate-stack DGMOSFETbased CMOS inverter”, International Journal of Nano Dimension 12 (2), 98-103.
14. B Jena, K Bhol, U Nanda, S Tayal, SR Routray, “Performance Analysis of Ferroelectric GAA MOSFET with Metal Grain Work Function Variability” SILICON, 1-8. .
15. S Tayal, J Ajayan, L. Joseph, D. Nirmal, B Jena, A. Nandi “A Comprehensive Investigation of Vertically Stacked Silicon Nanosheet Field Effect Transistors: an Analog/RF Perspective” SILICON. 3-9
16. K Bhol, B Jena, U Nanda, “Silicon Nanowire GAA-MOSFET: a Workhorse in Nanotechnology for Future Semiconductor Devices” SILICON.
17. K Bhol, B Jena , U Nanda, “Journey Of MOSFET From Planar To Gate All Around: A Review” RECENT PATENTS ON NANOTECHNOLOGY, DOI : 10.2174/1872210515666210719102855 (In Press)
18. S. Tayal, S. Bhattacharya, B. Jena, et al. Linearity Performance and Harmonic Distortion Analysis of IGE Junctionless Silicon Nanotube-FET for Wireless Applications. SILICON (2021). https://doi.org/10.1007/s12633- 021-01313-y.
19. K Mahidhar, S Rooban, S Tayal, B Jena, “An insight into the Performance Analysis of GAA MOSFET for Different Dielectrics at Cryogenic Temperatures”, Cryogenics, Vol. 122, 103425. (2022)
20. S. Panda, B. Jena, S. Dash, “Ambipolarity Suppression of a Double Gate Tunnel FET using High-k Drain Dielectric Pocket”, ECS J. Solid State Sci. Technol. 11 013014. (2022).
21. K Bhol, U Nanda, B Jena, S Tayal, SM Biswal, “Development of an analytical model of work function modulated GAA MOSFET for electrostatic performance analysis”, Phys. Scr. 97 024007. (2022)
Conference Papers
1. B. Jena, S. Dash, G.P Mishra, “An extensive simulation study of cylindrical surrounding gate MOSFET (DMCSG-MOSFET) with gate misalignment, " Michel Faraday IET International summit-2015, September 12- 13, 2015 at Hotel Hindustan International, Kolkata, India.
2. B. Jena, S. Dash, G.P Mishra, “An analytical Nanowire Tunnel FET (NW-TFET) model with high-k dielectric to improve the electrostatic performanc," IEEE Power, Communication and Information Technology Confer- ence (PCITC), October 15-17, 2015 at S ’O’ A Deemed to be University, Bhubaneswar, India.
3. B. Jena, S. Dash, G.P Mishra, RF analysis of work function modulated cylindrical surrounding gate MOSFET" at Devices for Integrated Circuit (DevIC), 2017, March 23-24, 2015 at Kalyani Govt. college, Kolkata, India.
4. TS Sasank, PR Ganesh, N P Kumar, B Jena, AJ Obaid, “Analysis of Static Noise Margin of 10T SRAM Using Sleepy Stack Transistor Approach" Ibn Al-Haitham International Conference for Pure and Applied Sciences (IHICPS), 2020, Dec 20-21, 2020 at University of Baghdad, Iraq.
5. K. Bhol, B. Jena, S. Tayal, UK Nanda, Work-Function modulated GAA MOSFET for Improved Electrostatic Controllability in Lower Technology Node " at Devices for Integrated Circuit (DevIC), 2021, May 19-20, 2021 at Kalyani Govt. college, Kolkata, India
6. TP Dash, E Mohapatra, B. Jena, CK Maity, Strained SiGe Channel TFTs For Flexible Electronics Applications " at Devices for Integrated Circuit (DevIC), 2021, May 19-20, 2021 at Kalyani Govt. college, Kolkata, India
7. UK Nanda, D Nayak, SK Saw, A Mazeed, B Jena, Analysis of Static Noise Margin of 10T SRAM Using Sleepy Stack Transistor Approach" at Devices for Integrated Circuit (DevIC), 2021, May 19-20, 2021 at Kalyani Govt. college, Kolkata, India.