Keynote

A Vision for Expandable Data Management Infrastructure and Acceleration with Heterogenous Configurable Systems

José Roberto Alvarez, Senior Director CTO Office Lead, Intel Programmable Solution Group

Coherently attached FPGAs will unlock the full potential of their configurable fabric by enabling expandable memory and bringing together the four components of a data management system – storage, memory, compute and network. In this configuration, the CPU can access the memory or storage attached to the FPGA coherently, while the reconfigurable fabric is able to support look-aside and inline acceleration for CPU/storage, CPU/memory, CPU/network, network/storage paths. Computational storage as well as computational memory will be facilitated by the same fabric that resides at the core of the heterogeneous compute systems. In this talk, we will present a vision of how heterogenous compute systems centered around FPGAs can help with TCO, performance and power density and the use cases that support such vision. We will present device features of the UPI/CXL enabled FPGA and platforms that connects to DDR, persistent memory, persistent storage and high-speed networks. In addition to device and platform features, we will discuss how a software developer will be able to use such a platform using OneAPI.

José Roberto Alvarez is Senior Director at Intel Programmable Solutions Group in San Jose, California, where he leads the Technology and Innovation CTO Office, defining and implementing long term FPGA research strategy and roadmaps. He started his career at Philips Laboratories and throughout his career he has been deeply engaged in architecting, designing and implementing technology products for a variety of industries including broadcast, embedded, consumer, post-production and computer graphics for companies including Philips, S3, Broadcom, Maxim, Xilinx, and four successful start-ups in Silicon Valley. His research interests include FPGA advanced architectures and development tools, immersive media technologies and volumetric coding. His work has been granted 53 patents.