[1] J.-F. Lin, Z.-J. Hong, C.-Y. Chan, B.-C. Wu, S.-W. Yu, "Novel Low-Complexity and Low-Power Flip-Flop Design," Electronics , vol. 9, pp. 783, 2020.
[2] J.-F. Lin, C.-Y. Chan, S.-W. Yu, "Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications," Electronics , vol. 8, pp. 1429, 2019.
[3] J.-F. Lin , S.-W. Yu, C.-M. Tsai and M.-H. Sheu, "A low voltage and low power flip-flop design using virtual VDD scheme," Journal of Semiconductor Technology and Science, vol. 19, no. 5, pp. 505-509, 2019.
[4] P.-Y. Kuo, C.-H. Hsieh, J.-F. Lin, M.-H. Sheu, and Y.-T. Hung, "Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design," IEICE Transactions on Electronics, p. 2018ECP5059,2019.
[4] J.-F. Lin, M.-Y. Tsai, C.-S. Chang, and Y.-M. Tsai, "A novel low power flip-flop design using footless scheme," Analog Integrated Circuits and Signal Processing, vol. 97, no. 2, pp. 365-370, 2018.
[5] J.-F. Lin and M.-Y. Tsai, "A Modified Static Contention Free Single Phase Clocked Flip-flop Design for Low Power Applications," Journal of Semiconductor Technology and Science, vol. 18, no. 5, pp. 640-644, 2018.
[6] J. F. Lin, M.-H. Sheu, Y.-T. Hwang, C.-S. Wong, and M.-Y. Tsai, "Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp. 3033-3044, 2017.
[7] J.-F. Lin, "Low Power Latch-adder Based Multiplier Design," Journal of Semiconductor Technology and Science, vol. 17, no. 6, pp. 806-814, 2017.
[8] J.-F. Lin, M.-Y. Tsai, K.-S. Li, Y.-R. Jiang, and Y.-S. Cheng, "Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors," Journal of low power electronics, vol. 12, no. 2, pp. 112-116, 2016.
[9] J.-F. Lin, Y.-C. Lee, W.-C. Lin, "Low Power Divider Design Using Pass Transistor Logic Circuit Schemes" ICIC Express Letters pp. 1547-1552 , 2016.
[10] J.-F. Lin, Y.-T. Hwang, C.-S. Wong, and M.-H. Sheu, "Single-ended structure sense-amplifier-based flip-flop for low-power systems," Electronics Letters, vol. 51, no. 1, pp. 20-21, 2015.
[11 ]J.-F. Lin, "Low-power pulse-triggered flip-flop design based on a signal feed-through," IEEE transactions on very large scale integration (vlsi) systems, vol. 22, no. 1, pp. 181-185, 2013.
[12]J.-F. Lin, "Low-power pulse-triggered flip–flop design using gated pull-up control scheme," Electronics letters, vol. 47, no. 24, pp. 1313-1314, 2011.
[13] Y.-T. Hwang, J.-F. Lin, and M.-H. Sheu, "Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme," IEEE transactions on very large scale integration (VLSI) systems, vol. 20, no. 2, pp. 361-366, 2011.
[14] Y.-T. Hwang and J.-F. Lin, "Low voltage and low power divide-by-2/3 counter design using pass transistor logic circuit technique," IEEE transactions on very large scale integration (vlsi) systems, vol. 20, no. 9, pp. 1738-1742, 2011.
[15]J.-F. Lin, Y.-T. Hwang, and M.-H. Sheu, "A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits," IEICE transactions on fundamentals of electronics, communications and computer sciences, vol. 93, no. 4, pp. 843-845, 2010.
[16] J.-F. Lin, Y.-T. Hwang, and M.-H. Sheu, "Low Power Pulse Generator Design Using Hybrid Logic," IEICE transactions on fundamentals of electronics, communications and computer sciences, vol. 93, no. 6, pp. 1266-1268, 2010.
[17] J.-F. Lin, Y.-T. Hwang, and M.-H. Sheu, "A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic," IEICE transactions on fundamentals of electronics, communications and computer sciences, vol. 93, no. 12, pp. 2755-2757, 2010.
[18] J.-F. Lin, Y.-T. Hwang, and M.-H. Sheu, "Low complexity dual-mode pulse generator designs," IEICE transactions on fundamentals of electronics, communications and computer sciences, vol. 91, no. 7, pp. 1812-1815, 2008.
[19] J.-F. Lin, Y.-T. Hwang, M.-H. Sheu, and C.-C. Ho, "A novel high-speed and energy efficient 10-transistor full adder design," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 5, pp. 1050-1059, 2007.
[1]Palm C. Chang CS., Lin JF., Lee MC. , “Semantic Lung Segmentation Using Convolutional Neural Networks”, Bildverarbeitung für die Medizin 2020 , Jan. 2020.
[2]Wei-Hsuan Ma, Kuan-Ying Chang, Kuan-Ting Chen, Yin-Tsung Hwang, Jin-Fa Lin, “Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation”, 2019 International SoC Design Conference (ISOCC) , Oct. 2019.
[3]林進發, 蔡長銘, 李明璟, 楊伊凡, 吳柏誠 "以自動化電腦辨識軟體評估胸部X 光之正常肺面積與臨床應用" , ILT2019, June 2019.(榮朝計畫)
[4]Jin-Fa Lin, Shao-Wei Yu, Chang-Ming Tsai and Zheng-Jie Hong, “A low voltage and low power true-signal-phase flip-flop design by using reduce the number of clocked transistors”, VLSICAD2019, Aug. 2019.
[5] 林進發,李崑生,韓國強,邢益勛,陳晁泰 “Bi-direction Low Cost Flexible Design of Sensing Panel on Conventional Seven-segment Display”, AIT Conference, May. 2019.
[6]Jin-Fa Lin, Zheng-Jie Hong, Yu-Min Chi, Ming-Ren Zhang, Po-Wei Wang, Ting-Kai XuA, “Low voltage and low power true-signal-phase flip-flop design Using Virtual VDD Scheme with 68% energy saving”, VLSICAD2018, Aug. 2018.
[7]Jin-Fa Lin, Ching-Sheng Chang, Wei-Jun Chien, Chang-En Cai and Qiu-Bo Yao, “Development of insect-trapping system implemented”, AIT, Apr. 2017.
[8]Jin-Fa Lin, Ming-Yan Tsai, Kun-Sheng Li, Yun-Rong Jiang, Yu-hsing Cheng, “A 19-transistor flip-flop design Using Footless Scheme with 82% Energy Saving”, VLSICAD2017, Aug. 2016.
[9]Wang, Shin-Shiang,Jin-Fa Lin, et al. "MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging." 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2016.
[10] Jin-Fa Lin, Ming-Yin Tsai, Chia-Hsuan Chen, Chiao-Lan Ku and Yu-Wei Chang, “A 19-transistor flip-flop design using pass transistor circuit scheme with 81% energy saving”, VLSICAD2015, Aug. 2015.
[11]林進發,蔣云容,鄭宇翔,李崑生, “具低複雜度與低功率消耗特性之正反器設計”, 2015民生電子研討會, Nov. 2015.
[12]洪顗婷,翁晨軒,許明華,林進發 “具有低功率與高效能之感測放大正反器設計與晶片實現”, 2015 Conference on Intelligent Electronics Designs and Applications, Nov. 2015.
[13]Jin-Fa Lin , Yu-Cheng Li, Yu-Wei Chang, Ming-Yen Tsai, Ciao-Lan Gu, “Low voltage and high performance divide-by-2 design using pseudo nMOS circuit scheme”, the 9th International Conference on Advanced Information Technologies/ Consumer Electronics Forum (AIT/CEF 2015), Apr. 2015.
[14] 林進發,陳韋谷,李育晟, “防止車門開啟意外之警示系統”, 2014 AIT Conference, Apr. 2014.
[15] 林進發,林文昌,葉威志,洪紳寶,李育晟, “適用於次臨界區操作之對稱式NAND閘”, 2014 AIT Conference, Apr. 2014.
[16] Dong-Ting Hu, Jin-Fa Lin, Chen-Syuan Wong, Jui-Yang Liao and Chia-Ching Chen, ”Low Power Counter Design Using Wired Logic Circuit Technique”, Apr. 2013.
[17] Jin-Fa Lin , Jui-Yang Liao, Dong-Ting Hu, Hung-Chi Chu, “A novel low power XNOR gate using symmetrical circuit technique for ultra low voltage applications”, International Conference on Advanced Information Technologies (AIT 2012).
[18] Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, “Low power 10-transistor full adder design based on degenerate pass transistor logic”, IEEE International Symposium on Circuits and Systems (ISCAS), May 2012.
[19] Jin-Fa Lin, Ming-Hwa Sheu, Peng-Siang Wang, “Pulse-triggered flip-flop design with PTL style control scheme, IEEE Region 10 Conference, Nov. 2011