Constraint Solving and Special Purpose Hardware Architectures

New Google Group: Hardware for Optimization

With the end of Moore’s Law and the success of GPUs in machine learning applications, hardware researchers have turned to special purpose, as opposed to general purpose, processor architectures. For classical computation, this had led to a number of chips from various manufacturers (e.g., Hitachi, Fujitsu) that solve specific classes of optimization problems in hardware. Simultaneously, the availability of early quantum chips (e.g., from IBM, Rigetti, and D-Wave) has raised the possibility of constraint solving using quantum computation. These hardware thrusts have resulted in a small but growing number of researchers exploring constraint solving on such hardware architectures. The goal of this workshop is to begin to develop a CP community by both bringing together these researchers and introducing the work to interested CPers.

Target Audience

Members of the broad CP community that

1. have begun investigating the use of special purpose hardware; or
2. are interested in learning about the hardware and early constraint-based research.

Format

We will have a combination of invited speakers and presentations based on submitted abstracts.

Invited Speakers

• Carleton Coffrin, Los Alamos National Laboratory
• Aidan Roy, D-Wave Systems
• Hayato Ushijima, Fujitsu Laboratories of America, Inc
• Davide Venturelli, NASA Ames
• Masanao Yamaoka, Hitachi Ltd