Weekly Status Updates

1-23-2020:

• Created website and initialized GitHub Repo.

1-30-2020:

• Downloaded VHDL Simulator and Vivado WebPack

2-6-2020:

• Completed Lab 1 part 1:
  • Cloned Professor Lu's GitHub repo for Lab 1 and created new Vivado project from the files. Ran the PnR flow and successfully loaded the bitstream on the FPGA.
  • Switches modify output.
• Developed 7-Segment Display driver:
  • Allows display of 1 digit/character per display.
  • Also allows for display of all alphabetical characters as well as most punctuation.
  • Implements scrolling for strings longer than 8 characters.

2-13-2020:

• Completed Lab 1 part 2:
  • Same as Lab 1 part 1. However, counting is now autonomous.
• Began Z80 ALU emulation (Verilog):
  • Currently controlled via switches on board.

2-20-2020:

• Assisted others with labs, troubleshot Xilinx simulation tool. Tool still broken.

2-27-2020:

• Completed Lab 2:
  • Can finally boot from configuration memory

3-5-2020:

• No Class, Professor in India

3-12-2020:

• Introduction to Online Classes. Simulated Lab 3.

3-19-2020:

• Spring Break

3-26-2020:

• Began online classes
• Determined Project. Details to be included on new project page.
  • Gameboy Emulator (GitHub Repo):
    • Target for the end of the semester: Fully emulate the Z80-based processor and output display of boot ROM to VGA Display.
    • Completed Register File and ALU infrastructure

4-1-2020:

• Improved software emulator to develop hardware verification infrastructure
  • Can generate bitstream stimulus for Verilog verification
• Created Build system (for simulation) and Verification infrastructure
• Developing schematics for data flow as reference for design

4-7-2020:

• Labs:
  • Beginning Lab 4
• "GameBuddy" GameBoy Emulator Final Project:
  • Discussed unpublished fine timing details of SM83 Architecture with Joonas Javanainen (Gekkio), leader of the effort to reverse engineer the GameBoy's cycle-exact implementation
    • Will add notes of discussion to GitHub repo when properly compiled
  • Implemented preliminary timing infrastructure for CPU
  • Reworked microarchitecture of the GameBuddy emulator as a result of my research and discussions
  • Reworked verification infrastructure to more easily debug the system later in the project
    • More comprehensive test vectors and tools to verify pipelined fetch decode/execute stages

4-9-2020:

• Added projects page to website
  • Added information about the GameBuddy project
• Explored Memory Interface Generation (MIG) tool in Vivado
  • Generated a DDR2 interface with 8-bit data, 16-bit address lanes, clocked at high speed to simulate GameBoy's Asynchronous memory
  • Implemented traffic generation module to test functionality
  • Due to this, I have re-architected memory access with two unidirectional data lanes and a single unidirectional address lane
• Performed research on tri-state buffering in FPGAs and controlling IOBUF tri-state features to interface CPU with memory buffer
• Updated Project page with timing information and timing diagrams for basic clock and decode functionality
  • Devised mock ups of CPU pipeline timing diagrams to implement in timing details section

4-16-2020:

• Spoke with Gekkio about bus architecture, T-Cycle timings, and memory access. The findings will be compiled into another document and pushed to the GitHub Repo.
  • Main Takeaways:
    • I will be scrapping idea to use DDR2 + MIG configuration, rather I will use the Artix-7's block RAM to emulate the GameBoy's asynchronous memory, as was Gekkio's suggestion.
      • This will also eliminate the need to use IOBUF tri-state functionality since the internal BRAMs have data_in and data_out ports, which does not require me to converge the two data buffers onto the same bidirectional data bus.
    • The SM83 core contains at least 2 8-bit temporary registers. For example, these could possibly be used during conditional calls to construct the target address, and if the condition evaluates as true, the value is copied to the program counter.
    • Many of the buffers and memory accesses have latch-like behavior. Because of this I can either describe them as latches, or simply trigger them on the deasserting edge of the memory's control signals.
    • The address bus is buffered in a similar way to the data bus. This allows for the DMA controller to access memory at the same time that the CPU samples its internal data bus.
    • Discussed race conditions and bugs in the GameBoy's architecture that result from bus design oversights.
• Remodeled Bus architecture to account for DMA controller accesses
  • Modeled GameBoy's Asynchronous memory to continue development while I come up for fix in FPGA that can use synchronous block RAM instead of distributed asynchronous RAM
• Implemented temporary registers in register file
• Outlining architecture for 16-bit registers

4-23-2020:

• GameBuddy GameBoy Emulator:
  • Successfully implemented the majority of the ALU module
  • Integrated decode for most operations and can effectively conduct Adds, Shifts, Rotates, and bitwise operations on registers
  • Updated alias files to show operations on waveform for better debugging
  • Implemented tasks to cover ALU dispatches and register write-back
  • Updated webpage to reflect progress with detailed documentation on decisions I have made
  • Implemented Flag register and modified ALU operation to affect flags
  • Began project ReadMe

4-30-2020:

• GameBuddy GameBoy Emulator:
  • Created assembly tools to generate binary programs from GB assembly files and generate random stimulus based on currently supported instructions
  • Fixed multiple bugs in both the software and hardware emulators as a result of this tool
  • Implemented more robust verification system to detect mismatches
  • Implemented 8-bit immediate memory reads and 8-bit addressed reads and verified functionality
• Labs:
  • Completed labs 4 and 5, will upload screenshot of generated bitstream as proof shortly

5-5-2020:

• GameBuddy GameBoy Emulator:
  • Implemented Memory writes, 16-bit Immediate loads, and all CB-prefixed instructions
  • MANY bug fixes in both the software and hardware emulators
  • Began implementation of a Stack Pointer to account for many of the currently uncovered instructions
  • Results in a total of 78% instruction coverage, which has been verified against my software emulator
• Labs:
  • Completed lab 6 over the weekend

Lab 4 Update:

• Leading Zero Suppression accomplished by modifying the leddec16.vhd file:

anode <=   "1110" when dig="00" and data /= X"0000" else -- digit 0

  "1101" when dig="01" and data(15 downto 4) /= X"000" else -- digit 1

  "1011" when dig="10" and data(15 downto 8) /= X"00" else -- digit 2

  "0111" when dig="11" and data(15 downto 12) /= X"0" else -- digit 3

  "1111";

• Subtraction accomplished by modifying hexcalc.vhd:

entity hexcalc is

  Port ( clk_50MHz : in STD_LOGIC;

    SEG7_anode : out STD_LOGIC_VECTOR (3 downto 0); 

   SEG7_seg : out STD_LOGIC_VECTOR (6 downto 0); 

     bt_clr : in STD_LOGIC;

    bt_plus : in STD_LOGIC;

      bt_eq : in STD_LOGIC; 

     KB_col : out STD_LOGIC_VECTOR (4 downto 1); 

     KB_row : in STD_LOGIC_VECTOR (4 downto 1 ); 

     bt_sub: in STD_LOGIC);

...

signal add: STD_LOGIC;

...

when ENTER_ACC => 

if kp_hit = '1' then

  nx_acc <= acc(11 downto 0) & kp_value;

  nx_state <= ACC_RELEASE;

 elsif bt_plus = '1' then

  nx_state <= START_OP;

  add <= '1'; 

 elsif bt_sub = '1' then 

  nx_state <= START_OP;

  add <= '0';

 else nx_state <= ENTER_ACC;

 end if;

...

when ENTER_OP =>

 display <= operand;

 if (bt_eq = '1' and add = '1' )then

   nx_acc <= acc + operand;

  nx_state <=SHOW_RESULT

 elsif (bt_eq = '1' and add = '0' )then

  nx_acc <= acc - operand;

  nx_state <= SHOW_RESULT;  

 elsif kp_hit = '1' then

  nx_operand <= operand(11 downto 0) & kp_value;

  nx_state <= OP_RELEASE;  

 else nx_state <= ENTER_OP;

 end if;

• I/O Constraints were also modified to accommodate this change.

Code changes are becoming larger and can be seen in the GitHub Repo for my labs.

Lab 5 Update:

• Generated Bit Stream
• Modified tone module to create a square wave
• Changed wailing speed
• Modified constraint file to allow Switches 0-7 to control wailing speed
• Changed upper and lower pitch limits
• Added a second instance of wail to drive the right audio channel.
  • Used different high and low tone limits and wailing speed for the right audio channel

Lab 6 Update:

• Generated Bit Stream
• Modified bat_n_ball.vhd to allow for ball speeds of 1-32 pixels per frame
• Modified bat_n_ball.vhd to render larger and smaller bat sizes
• Change bat size with each successful hit
  • New signal implemented to indicate successful hit. Decrements bat size on next cycle
  • Underflow leads to bat size reset

5-12-2020:

• Finals, no progress made on GameBuddy
• Documentation improvements, final DSD pushes to GameBuddy repository