Event

SCA/HPCAsia2026 BOF

Date: January 29 (Thu), 2026

Time: 11:30AM - 12:30PM (Japan)

Room: 1101

Link to SCA/HPCAsia program

Special invited speakers: Lilia Zaourar (CEA), Toru Niina (RIKEN), James Ang (PNNL)

Session leaders: Kazutomo Yoshii (ANL), Kentaro Sano (RIKEN), and John Shalf (LBNL)

Future chip development needs more compute. HPC has plenty. It’s time they work together. Innovation in chip design is crucial for the future of computing. This BoF aims to foster such innovation by significantly improving the chip design and verification process through the computational power of HPC. As demand for specialized architectures grows in the post-Moore era, this session explores how HPC resources and AI-assisted workflows are transforming chip prototyping. Participants will discuss domain-specific accelerators, open-source tools, and HPC-enabled workflows for design, verification, simulation, and emulation, fostering collaboration between HPC and architecture communities.

Topics

AI-assisted hardware design workflows: applying AI to RTL generation, verification, and layout, and exploring compiler infrastructures such as CIRCT and MLIR for design automation.
HPC-enabled chip prototyping: using HPC clusters for large-scale RTL and multi-physics simulation, and employing FPGA clusters for fast emulation and architectural validation.
Feedback between HPC and architecture research: using real HPC applications to guide accelerator design, and studying chip prototyping itself as an emerging HPC workload.
Community collaboration and open toolchains: identifying gaps in open-source EDA flows (e.g., Chisel, Verilog-to-GDS) and promoting cross-community efforts between architecture researchers, EDA developers, and HPC practitioners.

The proposed session format is a 1-hour interactive BoF consisting of a 10-minute overview and motivation, 20 minutes of short position talks from academia, laboratories, and open-source communities, followed by 20 minutes of open discussion and brainstorming on shared needs and research directions, summary and next-step planning.

As the demand for performance and energy efficiency rises in the post-Moore era, this BOF session explores the transformative role of domain-specific accelerators and open-source hardware tools for HPC and scientific edge computing. Join us as we examine emerging trends, challenges, and opportunities in architecture research and chip prototyping.

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