Journals
Yuan-Ho Chen, Yu-Jie Yen, Chin-Fu Nien* (*: corresponding author), Chao-Sung Lai, “Efficient Power- and Area-Optimized 800-Spin Ising Chip for Solving Combinatorial Optimization Problems Using Multirun Decremental Annealing, ” IEEE Internet of Things Journal, vol. 12, no. 20, pp. 42965-42974, Oct. 2025.
Yuan-Ho Chen, Che-An Chou, Chin-Fu Nien* (*: corresponding author), and Shinn-Yn Lin, “Design and Implementation of a Very-Large-Scale Integration–Based Annealing Accelerator for Efficiently Solving Combinatorial Optimization Problems,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 9, pp. 4291-4295, Sept. 2024.
Yen-Jui Chang, Chin-Fu Nien, Kuei-Po Huang, Yun-Ting Zhang, Chien-Hung Cho, and Ching-Ray Chang, “Quantum Computing for Optimization with Ising Machine,” IEEE Nanotechnology Magazine, vol. 18, no. 3, pp. 15-22, June 2024.
Yuan-Ho Chen, Hsin-Tung Hua, Chin-Fu Nien* (*: corresponding author), and Shinn-Yn Lin, “VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems,” IEEE Nanotechnology Magazine, vol. 18, no. 3, pp. 23-30, June 2024.
Lien-Po Yu and Chin-Fu Nien* (*: corresponding author), "Physics-inspired Optimization in the QUBO Framework: Key Concepts and Approaches," SPIN, vol. 13, no. 4, article 2340016, 2023.
Tsung-Hsuan Tsai, YiChing Chen, and Chin-Fu Nien, “Network Bandwidth Utilization Optimization with Quantum-Inspired Approach,” SPIN, vol. 13, no. 4, article 2340015, 2023.
Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, and Chin-Fu Nien, “DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators,” ACM Transactions on Embedded Computing Systems, vol. 21, no. 3, article 24, pp. 1–29, May 2022.
Sheng-Fu Hsiao, Chin-Fu Nien, Dan Chen, and Ching-Jan Chen, “Four-Frequency Small-Signal Model for High-Bandwidth Voltage Regulator with Current-Mode Control,” IEEE Access, vol. 10, pp. 25633–25644, Feb. 2022.
Le Kong, Dan Chen, Sheng-Fu Hsiao, Chin-Fu Nien, and Guang-Feng Li, “A Novel Adaptive-Ramp Ripple-based Constant On-Time Buck Converter for Stability and Transient Optimization in Wide Operation Range,” IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 6, no. 3, pp. 1314–1324, Sept. 2018.
Chin-Fu Nien, Dan Chen, Sheng-Fu Hsiao, Le Kong, Ching-Jan Chen, Wei-Hao Chan, and Yen-Liang Lin, “A Novel Adaptive Quasi-Constant On-Time Current-Mode Buck Converter,” IEEE Transactions on Power Electronics, vol. 32, no. 10, pp. 8124–8133, Oct. 2017.
Conferences
Cing-Yuan Lai, Chin-Fu Nien * (corresponding author), Lien-Po Yu, Chao-Sung Lai, “Mixed-precision Neural Network Quantization with Quantum-inspired Annealers,” 2025 International SoC Design Conference (ISOCC), 2025 (accepted).
Tsung-Yu Liu, Yen An Lu, James Yu, Chin-Fu Nien* (*: co-corresponding author), and Hsiang-Yun Cheng *, “ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis,” 29th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025. (28.62% acceptance rate)
Yu-Tzu Chen, Chin-Fu Nien* (corresponding author), Chin Hsia, and Chung-Yi Li, “Interactive Analog IC Layout Tool with Real-time Parasitic-aware Automatic Routing Assistance,” 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2024, pp. 149-153.
Yung-Cheng Lai and Chin-Fu Nien* (corresponding author), “An Automated Design Platform for ReRAM-based DNN Accelerators with Hardware-Software Co-exploration,” 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2024, pp. 144-148.
Kuei-Po Huang and Chin-Fu Nien* (corresponding author), Yun-Ting Zhang, Cheng-Kuang Lee, Yu-Cheng Wang, “GPU-based Ising Machine for Solving Combinatorial Optimization Problems with Enhanced Parallel Tempering Techniques,” 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2024, pp. 636-640.
Hao-Wei Chiang, Chin-Fu Nien* (*: co-corresponding author), Hsiang-Yun Cheng*, Kuei-Po Huang, “ReAIM: A ReRAM-based Adaptive Ising Machine for Solving Combinatorial Optimization Problems,” 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), Buenos Aires, Argentina, 2024, pp. 58-72. (19.6% acceptance rate)
Yun-Ting Zhang, Chin-Fu Nien, Chia-Wei Lin, Wen-Jui Chao, Chen-Yu Liu, Lien-Po Yu, and Yuan-Ho Chen, “An Automated Toolchain for QUBO-based Optimization with Quantum-inspired Annealers,” 20th International SoC Design Conference (ISOCC), Jeju, Korea, Republic of, 2023, pp. 171-172.
Chung-Yi Li, Chin-Fu Nien, Li Lin, and Hung-Chi Chen, “A Generalized Current Balancing Control for Series-Capacitor Buck Converter with Interleaved Phase Angle,” 2023 IEEE 24th Workshop on Control and Modeling for Power Electronics (COMPEL), Ann Arbor, MI, USA, June 2023.
Ting Wu, Chin-Fu Nien, Kuang-Chao Chou, and Hsiang-Yun Cheng, “RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment,” 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, Mar. 2022, pp. 400–405. (23% acceptance rate)
Cheng-Yang Tsai*, Chin-Fu Nien* (*: equal contribution), Tz-Ching Yu, Hung-Yu Yeh, and Hsiang-Yun Cheng, “RePIM: Joint Exploitation of Activation and Weight Repetition for In-ReRAM DNN Acceleration,” 2021 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Dec. 2021, pp. 589–594. (23% acceptance rate)
Yi-Jou Hsiao, Chin-Fu Nien, and Hsiang-Yun Cheng, “ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator,” 2021 IEEE 39th International Conference on Computer Design (ICCD), Storrs, CT, USA, Oct. 2021, pp. 260–268. (24% acceptance rate)
Chin-Fu Nien, Yi-Jou Hsiao, Hsiang-Yun Cheng, Cheng-Yu Wen, Ya-Cheng Ko, and Che-Ching Lin, “GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing,” 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, Mar. 2020, pp. 1478–1483. (26% acceptance rate)