Publication
Peer-Reviewed Journals
J7. [Nature Scientific Reports '2022] Fully integrated topological electronics
Yuqi Liu, Weidong Cao*, Weijian Chen, Hua Wang, Lan Yang, Xuan Zhang*
Scientific Reports volume 12, Article number: 17010 (2022). Equal contribution and correspondence.
News: [MIT Technology Review] (Chinese).
J6. [Nature Nanotechnology '2022] Fully integrated parity–time-symmetric electronics
Weidong Cao, Changqing Wang, Weijian Chen, Song Hu, Hua Wang, Lan Yang, Xuan Zhang
Nature Nanotechnology 17, 262–268 (2022), [pdf], [pdf_arXiv].
News: [Phys.org], [Mirage News], [True Viral News], [Bioengineer.org], [ScienMag], [Newswise], [Nanowerk], [MIT Technology Review] (Chinese).
J5. [TC '2021] Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals
Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang
IEEE Transactions on Computers, vol. 71, no. 9, pp. 2142-2155, 2022, [pdf].
News: [WashU News], [ScienceDaily], [Tech Xplore], [ScienMag].
J4. [TCAD '2021] Evaluating Neural Network-Inspired Analog-to-Digital Conversion With Low-Precision RRAM
Weidong Cao, Liu Ke, Ayan Chakrabarti, Xuan Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 5, pp. 808-821, 2021, [pdf].
J3. [TCAD '2020] NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion
Weidong Cao, Xin He, Ayan Chakrabarti, Xuan Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 1, pp. 1841-1854, 2020, [pdf].
J2. [Microelectronics journal '2018] A power scalable 2–10 Gb/s PI-based clock data recovery for multilane applications
Fangxu Lv, Xuqiang Zheng, Feng Zhao, Jianye Wang, Shigang Yue, Ziqiang Wang, Weidong Cao, Yajun He, Chun Zhang, Hanjun Jiang, Zhihua Wang
Microelectron. J. 82 (2018) 36–45, [pdf].
J1. [Microelectronics '2015] Design and implementation of a 20GHz VCO
Weidong Cao, Chenlong Hou, Jinxing Guo, Yilin Song, Ziqiang Wang, Hanjun Jiang, Zhihua Wang
Microelectronics, 2015, 5, 577-580.
Peer-Reviewed Conferences
C16. [DAC '2023] RoSE: Robust Analog Circuit Parameter Optimization with Sampling-Efficient Reinforcement Learning
Jian Gao, Weidong Cao*, Xuan Zhang*
IEEE/ACM Design Automation Conference (DAC), 2023. Equal contribution and correspondence.
Acceptance rate: 23%.
C15. [ISCA '2023] LeCA: In-Sensor Learned Compressive Acquisition for Efficient Machine Vision on the Edge
Tianrui Ma, Adith Jagadish Boloor, Xiangxing Yang, Weidong Cao, Patric Williams, Nan Sun, Ayan Chakrabarti, Xuan Zhang
International Symposium on Computer Architecture (ISCA), 2023.
Acceptance rate: 21.2%.
C14. [ICLR '2023] CktGNN: Circuit Graph Neural Network for Electronic Design Automation
Zehao Dong, Weidong Cao, Muhan Zhang, Dacheng Tao, Yixin Chen, Xuan Zhang
International Conference on Learning Representations (ICLR), 2023. Equal contribution.
Acceptance rate: 31.8%.
C13. [ISCAS '2023] A/D Alleviator: Reducing Analog-to-Digital Conversions in Compute-In-Memory with Augmented Analog Accumulation
Weidong Cao, Xuan Zhang
Accepted, IEEE International Symposium on Circuits and Systems (ISCAS), 2023, oral.
Invited to TCAS-II Special Issue.
C12. [ISCAS '2023] Non-Hermitian Physics-Inspired LC VCOs with Enhanced Frequency Tuning Range and Phase Noise Performance
Weidong Cao, Hua Wang, Xuan Zhang
Accepted, IEEE International Symposium on Circuits and Systems (ISCAS), 2023, oral.
Invited to TCAS-II Special Issue.
C11. [ICCAD '2022] PowerTouch: A Security Objective-Guided Automation Framework for Generating Wired Ghost Touch Attack on Touchscreens
Huifeng Zhu, Zhiyuan Yu, Weidong Cao, Ning Zhang and Xuan Zhang
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022.
Acceptance rate: 24%.
C10. [ISLPED '2022] HOGEye: Neural Approximation of HOG Feature Extraction in RRAM-Based3D-Stacked Image Sensors
Tianrui Ma, Weidong Cao, Ayan Chakrabarti, Xuan Zhang
ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2022.
Acceptance rate: 28%, Best Paper Awardee.
C9. [DAC '2022] Domain Knowledge-Infused Deep Learning for Automated Analog/RF Circuit Parameter Optimization
Weidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma
IEEE/ACM Design Automation Conference (DAC), 2022.
Acceptance rate: 23%, Best Paper Nominee.
C8. [AAAI '2022] Domain Knowledge-based Automated Analog Circuit Design with Deep Reinforcement Learning
Weidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma
36th AAAI Conference on Artificial Intelligence workshop, 2022.
C7. [ICCAD '2019] Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM Devices
Weidong Cao, Liu Ke, Ayan Chakrabarti, Xuan Zhang
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019.
Acceptance rate: 23.9%, Best Paper Nominee of the Track.
C6. [DATE '2019] NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization Support
Weidong Cao, Xin He, Ayan Chakrabarti, Xuan Zhang
IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
Acceptance rate: 24%, Best Paper Nominee.
C5. [NEWCAS '2016] A 28 Gb/s Transmitter with 3-tap FFE and T-coil Enhanced Terminal in 65 nm CMOS Technology
Naiwen Zhou, Linghan Wu, Ziqiang Wang, Xuqiang Zheng, Weidong Cao, Chun Zhang, Fule Li, Zhihua Wang
IEEE International New Circuits and Systems Conference (NEWCAS), 2016.
C4. [MWSCAS '2015] A 40Gb/s 39mW 3-tap Adaptive Closed-loop Decision Feedback Equalizer in 65nm CMOS
Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2015.
C3. [NEWCAS '2015] A 40 Gb/s 27 mW 3-tap Closed-loop Decision Feedback Equalizer in 65 nm CMOS
Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang
IEEE International New Circuits and Systems Conference (NEWCAS), 2015.
C2. [EDSSC '2015] A 40 Gb/s Adaptive Equalizer with Amplitude Approaching Technique in 65 nm CMOS
Weidong Cao, Ziqiang Wang, Dongmei Li, Fule Li, Zhihua Wang
IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015.
C1. [EDSSC '2015] A 15 Gb/s Wireline Repeater in 65 nm CMOS Technology
Weidong Cao, Xuqiang Zheng, Ziqiang Wang, Dongmei Li, Fule Li, Shigang Yue, Zhihua Wang
IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015.