Hardware

Train Control System

VHDL, UML Diagramming

In this simulation, Train A traverses clockwise along the outer track, and on every other lap, switch 3 (sw3) flips and redirects Train A on the L shaped track. Train B travels counter clockwise along the inner loop and never leaves it. Because the trains can travel at different speeds, one train must hold at one of the sensors (S1-S6) if the other train is either occupying a shared track or is on a track that crosses with the train's current track. To approach this, I gave each track segment (track between sensors) a number, and drew diagrams for each possible train position case. Using these diagrams and the information from the sensors, I formulated a finite state machine consisting of general position states and wait states where one train stops to wait for the other train to clear the segement. The state machine diagram was then implemented in VHDL and tested on the lab computers to insure it was collision free.