Research
Doctoral Student Researcher
Research conducted on point-of-care (POC) applications based on the Doppler blood flow spectrogram waveform of the peripheral arteries for reducing some forms of cardiovascular risks factors. The overall goal is to propose a low-cost diagnostic system for improving healthcare services.
Smartphone based low-cost portable continuous-wave Doppler Ultrasound system
The researchers of VLSI CAD Lab (including the author) at IIT Kharagpur have developed a prototype of smartphone based portable continuous-wave Doppler Ultrasound (US) system. The proposed system includes analog front end (AFE), signal processing and display unit (SPDU) and smartphone application. The AFE acquires blood flow signal from the Brachial artery using an 8 MHz pencil transducer probe, extracts Doppler shift frequency and transfers to the SPDU through analog to digital converter. SPDU is embedded in a FPGA based single chip where CORDIC based 512-point Fast Fourier Transform is implemented for displaying the spectrogram waveform in real-time. The smartphone application receives a spectrogram through Bluetooth, removes noise, extracts hemodynamic features and validates with that of the standard US instrument. The hand-held device is cost-effective, minimally trained operator-dependent and consumes < 4 W of power for real-time processing.
Cuffless pressure (BP) and Heart rate (HR) estimations using portable Doppler Ultrasound system
A cuffless BP and HR estimation technique has been proposed using the portable Doppler US system. The US blood flow signal obtained from the peripheral artery is denoised using soft thresholding method. To extract hemodynamic features, the spectrogram envelope of maximum frequency is obtained by an signal noise slope intersection (SNSI) approach. The 2-element Windkessel (WK) model is employed for BP estimation while a machine learning algorithm determines the WK model parameter values. The experimental results are compared with that of the international standard protocols for performance analysis. The robustness of the approach is also examined using pre-exercise and post-exercise performance. The proposed approach is non-invasive, non-occlusive and worthy of implementation as a portable system for POC application.
Peripheral artery disease (PAD) detection
A low-cost diagnostic method is proposed for detecting the severity of PAD based on the hemodynamic features of the Doppler blood flow spectrogram waveform (obtained from lower limb arteries). The different types of irregular blood flow in the arterial segments are analyzed to diagnose the condition of the healthy and diseased arteries. The zone of hemodynamically significant obstruction is detected. Moreover, the arterial diameter reduction is graded for the quantification of stenoses. Finally, a smartphone application is implemented to explore the role in POC diagnostic tests which might be useful to support public health interventions, primarily in rural and remote health services.
Hardware implementation for arterial disease diagnostic system
A VLSI design is introduced to implement the arterial disease detection scheme. The proposed method consists of spectrogram image binarization using Otsu’s thresholding, selected features extraction and automated diagnosis using a SVM based machine learning classifier. The design of the entire diagnostic system is implemented on FPGA for a single chip solution. To simplify the computational complexity, a memory based logarithmic function is proposed which is used in the Otsu’s thresholding method as well as features extraction technique to avoid multiplication and division operations. The proposed logarithmic converter is simple, avoids any mathematical computation and provides a faster operation. The logarithmic feature values are employed to train the SVM model in offline for obtaining the decision function.
Master Student Researcher
Design and application of hybrid Single electron transistor (SET) with CMOS in VLSI technology. The overall goal is to obtain ultra low-power consumption using SET device and high switching speed using CMOS technology.
Hybrid SET-CMOS integrated circuit based co-simulation
The hybrid technology is formed by replacing NMOS transistor by SET and PMOS acting as the load resistance of a SET. The CMOS–SET inverter is realized for transfer characteristics and noise immunity analysis. Moreover, hybrid technology is used for designing logic gates (NAND, NOR, XOR), different types of counter and register, reversible logic gates and ALU. The hybrid technology exhibits superior performance (power and delay analysis) compared to conventional CMOS technologies.
Multi-gate hybrid SET-CMOS modelling in 22nm technology
The multi-input SET is integrated with MOSFET for faster switching speed than a conventional one. The proposed multigate hybrid SET-CMOS model is investigated at room temperature and its electrical phenomena (Coulomb Oscillation and Coulomb Blockage) are verified using SIMON simulator tool. The multigate SET characteristics (IDS–VDS and IDS–VGS) have been proposed in wide temperature range. Moreover, the co-simulation of hybrid SET-MOS in 22nm technology has been used for designing logic circuits. A comparative study of power consumption and switching time are measured for performance analysis.