Research Motivations:

• Addressing Existing Neural Interface Limitations: Neuromorphic neural interface SoCs aim to solve issues related to signal delay, high power use, and limited processing capacity in current systems.

• neuron-like Efficiency: By mimicking the neural circuits, these SoCs seek to process information more efficiently with lower energy consumption.

Research Outlook:

• Improved Rehabilitation and Assistive Tech: These SoCs promise enhanced support for individuals with sensory impairments or neural damage, improving their quality of life.

• Energy Efficiency: Neuromorphic designs are geared towards using much less energy than traditional systems, ideal for devices where power conservation is key.

• Ongoing Innovation: The field is rapidly advancing, with interdisciplinary research paving the way for new breakthroughs that could significantly impact human life.

Our research focuses on the integration of neuromorphic processors with neural interface SoCs (e.g., artificial retinas, cochlear implants) to achieve ultra-low power consumption and precise communication with sensory neural networks. This work aims to significantly improve the quality of life for patients.  

Reference

• Jeong Hoan Park, Joanne Si Ying Tan, Han Wu, Yilong Dong, and Jerald Yoo, “1225-Channel Neuromorphic Retinal-Prosthesis SoC with Localized Temperature-Regulation”, IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no .6, pp.1230-1240, 2020.

• Jeong Hoan Park, Joanne Si Ying Tan, Han Wu, Jerald Yoo,  “1225-Channel Localized Temperature-Regulated Neuromorphic Retinal-Prosthesis SoC with 56.3nW/Channel Image Processor,” IEEE International Solid- State Circuits Conference - (ISSCC) Dig. Tech. Papers, Feb. 2020.

Research Motivations:

• EDM Equipment Access Challenges: Increasing complexity and density of modern chip designs have made accessing Electronic Design Manufacturing (EDM) equipment more difficult. This drives the need for innovative in-situ testing solutions to ensure comprehensive validation without relying heavily on external resources.

• Need for Built-in Test Circuits Due to Rising I/O Count: As the number of I/O ports in chiplets increases, there's a growing necessity for built-in test circuits. These circuits allow efficient testing within the chiplet, addressing limitations of traditional methods that struggle with expanded I/O requirements.

Research Outlook:

• Enhanced Autonomy in Testing: Developing high-speed DFT techniques will enhance the autonomy of testing processes, reducing dependence on EDM equipment and streamlining the production pipeline.

• Scalability and Integration Efficiency: Implementing built-in test circuits will improve the scalability and integration efficiency of chiplets, ensuring comprehensive testing in complex multi-chiplet configurations.

• Energy and Cost Efficiency: High-speed DFT methods lead to more energy-efficient testing processes and substantial cost savings by reducing reliance on external EDM equipment.

• Cell-based Design with EDA Tools: Utilizing cell-based design approaches and maximizing the use of Electronic Design Automation (EDA) tools will enhance design flexibility and optimization, leading to more efficient and effective test circuits.

• Self-Healing Capabilities: Incorporating self-healing functions into chiplets can detect and repair faults autonomously, significantly improving the reliability and longevity of semiconductor devices.

Our research focuses on developing and integrating high-speed DFT techniques for chiplets to enable rapid and reliable in-situ testing. By embedding advanced test circuits to handle rising I/O counts, utilizing cell-based design with EDA tools, and incorporating self-healing capabilities, we aim to enhance the testing phase's efficiency and effectiveness. This supports the semiconductor industry's need for high-performance, scalable, and cost-effective testing solutions, ultimately advancing next-generation electronic devices.

Reference

• in progress :-)