Mr. BHAWANAND JHA

 Mr. Bhawanand Jha

Assistant Professor

Bharati Vidyapeeth's College of Engineering, New Delhi

bhawanand.jha@bharatividyapeeth.edu

Office Phone: (011) 25258637,25278443 Extn.: - 

Qualification: 

• Ph.D. Pursuing

• M.Tech

• B.E.

Area of Specialisation: 

• Low power VLSI Design

• CMOS circuits integrated design

Work Experience: 

• Teaching: 10+ Yrs

Subjects Taught: 

• VLSI Design

• Electronic Devices

• Switching Theory and Logic Design

• Analog electronics – I

• Control system

• NAS

• MPMC

Paper Published:

• Bhawanand Jha, Kirti Gupta, and Rajeshwari Pandey, "Low Voltage Schmitt Trigger 4:1 Multiplexer Design for Portable Devices with Enhanced Performance," 12th International Conference on Computing for Sustainable Global Development (INDIACom), Delhi, India, pp. 1-6, 2025.

• Bhawanand Jha, Rajeshwari Pandey, Kirti Gupta, “High-performance noise-tolerant DTMOS Domino Schmitt trigger logic gate design”, Integration, Volume 103, 2025.

• Bhawanand Jha, Kirti Gupta, and Rajeshwari Pandey, "Low leakage Schmitt trigger logic circuits design with improved noise immunity for energy-constrained applications," International Journal of Electronics, pp.1-21, 2025.

• B. Jha, K. Gupta and R. Pandey, "Low Voltage Schmitt Trigger Full Adders Design for High Noise Immunity," 2022 8th International Conference on Signal Processing and Communication (ICSC), Noida, India, 2022, pp. 618-623, doi: 10.1109/ICSC56524.2022.10009098.

• B. Jha, K. Gupta and N. Pandey, "Multiple Threshold CVSL Full Adder Design," 2019 6th International Conference on Computing for Sustainable Global Development (INDIACom), New Delhi, India, 2019, pp. 74-77.

Seminar/Conference/FDP/Workshop Attended: 10

Seminar/Conference/FDP/Workshop Organized: 2

Other Activities:

• Conducted workshop on  PCB design and IoT

• Organized FDP on recent advancements in ML & AI

• Organized Alumnizoid for third year students

• Conducted Winter training  on IoT, ML & AI

• Qualified Gate exam three times