UFS (Universal Flash Storage)

UFS Serial Interface 

• the demand for speed and cost has led to parallel communication links becoming deprecated in favor of serial links.

• Speed:

  • Clock skew reduces the speed of every link.

  • Crosstalk creates interference between the parallel lines

• Cost: The decreasing cost of integrated circuit

UFS AsyncCommand & Command Queuing 

UFS Protocol Layer

UFS Architecture 2

M-PHY

Each 1LANE

• Normal Speed :

  • PWM-G0 ~ PWM-G7 : PWM G1 : 3 ~ 9Mbps

• HS-G1 ~ HS-G3( High Speed )

  • HS-G1 : (1.25Gbps or 1.45Gbps)

  • HS-G2 : (2.5Gbps or 2.9Gbps)

  • HG-G3 : (5Gbps or 5.8Gbps)

• TYPE I : PWM Signaling in UFS 1.0

• TYPE II : system Clock Reference(NRZ Signaling)

• UFS 1.0(currently) :

  • 2.9Gbps(HS-G2) & 1.45Gbps(HS-G1)

  • Extensible by lane increase in pairs

  • Each lane’s speed is 2.9Gbps(HS-G2).

    1. So, ideal bi-directional speed is double of this

  • Interface of card type UFS is same as M-PHY of embedded UFS. So, host side implementations (HW, SW) have no difference

UNIPRO ( Unified Protocol )

• Optimized

  • For mobile use cases & multiple applications

  • Low power & small battery-powered systems

• Enables minimized/extendable implementations

• Reliability with error detection and correction via retransmission simplifies protocol design

• Optimally uses MIPI’s PHY technologies

  • Allows aggressive power optimization

  • Allows for bandwidth scaling options

• Formal UniPro SDL model available

• UniPro testing specification available

UTP

• highestHW Layer

• SLOT: HW Resource for Command Acceptance

• 32 CMD Slots, 8 Task Slot, 1 Query Slot Each Slot has it’s own DESC.(Description of operation)

Hardware vs. Software

UFS Standardization

UFS UPIU Transaction Type

UFS Command Flow

d   Read Operation Flow 

Write Operation

UFS : Simple PCB routing and cost save 

SCSI Command & Operation