Research InterestS

Overview

AXIS Design Laboratory advances mixed‑signal integrated circuits for ultra‑low‑power, high‑accuracy sensor interfaces, power management and energy‑harvesting, data converters, and in‑sensor/edge computing. Our mission is to deliver reproducible precision, system‑level energy efficiency, and field robustness from silicon to real‑world deployment.

Research Themes

1) Precision Analog & Sensor Interfaces

We design low‑power, low‑drift analog front‑ends for environmental, industrial, and biomedical sensing. Emphasis is placed on accuracy over temperature and lifetime, high input impedance, and robustness to interference.
Focus areas: precision amplification, reference/bias generation, high‑impedance readout, calibration and system‑level linearity.

2) Data Converters (ADC/DAC)

We develop energy‑efficient data converters tailored to sensing and instrumentation. Architectures are chosen per application to achieve high effective resolution at low supply voltages, and are co‑optimized with analog front‑ends and digital post‑processing.
Focus areas: converter‑system co‑design, dynamic‑range management, background calibration, verification from behavioral models to silicon.

3) Power Management ICs & Energy Harvesting

Our PMIC research enables battery‑constrained or battery‑free operation in distributed sensors and edge devices. We study autonomous start‑up, adaptive power‑tracking algorithms, and multi‑mode DC‑DC conversion with integrated protection and safety. We also develop on‑chip regulation using low‑dropout regulators (LDOs) and precision references (bandgap references, BGRs) that interface cleanly with harvester/PMIC subsystems. In addition, we research power delivery for AI servers and HBM stacks, including high‑level studies of VRM/point‑of‑load regulation, μLDO arrays, and power‑integrity‑aware control.

Focus areas: start‑up for energy‑scarce sources; maximum‑power‑tracking control; mode‑transition efficiency; on‑chip regulation (LDOs); precision reference generation (BGRs); reliability and EMI awareness; AI Server/HBM power delivery.

4) In‑Sensor Computing & Edge AI

We explore near‑sensor analog pre-processing and low‑overhead feature extraction to reduce data movement and energy. Designs are co‑optimized with the sensing modality and the downstream digital pipeline.
Focus areas: analog‑domain preprocessing, event‑driven capture, standardized interfaces for photonic, resistive, and capacitive sensors.