Central Processing Unit

Control Unit

• controls interactions and data flow in the CPU
• manages responses to instructions

Arithmetic/Logic Unit

• performs calculations and logical operations
• values are placed in the Accumulator after calculation

Registers

see Types of Registers

• internal memory locations; all data must be stored in registers before it can be processed

Memory Unit

• consists of primary / main memory: RAM
• fast and directly accessible by the CPU; loading from RAM is faster than loading from secondary storage

RAM

• RAM is split up into many indexes, each index contains its own unique address and contents (in binary)

General purpose

Registers that hold data before and after it has been processed.

• used for many operations such as addition, subtraction, etc; hence 'general'.

Differences

• general purpose registers are smaller than special purpose registers
• general purpose registers can store both data and addresses

Other details

Operand

• part of an instruction which specifies what data is to be manipulated or operated on
• the data itself is also represented

Immediate Access Storage

• also known as RAM, is used to store programs and data

Special purpose

Registers that are dedicated to a specific use.

Program counter [PC]

• contains the address of the next instruction to be executed

Memory data register [MDR]

• stores the data being transferred to and from the immediate access storage

Memory address register [MAR]

• stores the memory address from which data will be fetched by the CPU

Index register

• used for modifying the addresses of operands
• contents of an index register is added to (in some cases subtracted from) an immediate address
  • this forms the location of a new address that can be located

Current instruction register [IR]

• holds the instruction currently being executed or decoded

Status register

• contains information about the state of the processor
• bits in the register are called flags

Common flags

zero flag

• indicates that the result of an arithmetic or logical operation (or, sometimes, a load) was zero

carry flag

sign / negative flag

• indicates that the result of a mathematical operation is negative

overflow flag

• indicates that the signed result of an operation is too large to fit in the register width using two's complement representation

Control Unit (CU)

• controls interactions and data flow in the CPU
• manages responses to instructions

Arithmetic / Logic Unit (ALU)

• performs calculations and logical operations
• values are placed in the Accumulator after calculation

Control bus

• bidirectional; transmits a signal from the Control Unit to another component or vice versa
• typically has 8 wires
• majorly used for carrying timing signals from the system clock

Data bus

• bidirectional; can send data to and from
• carries data to and from the processor; may be an instruction, address or value
• will also carry data from input devices either directly to memory or CPU, depending on the system

Word length

Also known as word size.

• the number of bits that can be processed at once
• data bus size, instruction size, address size are usually multiples of the word size
• typically 32 or 64 bits

Bus width

• increasing the number of wires, the bus width, will increase the amount of data the bus can carry at any one time
  • this speeds up the rate of processing

Clock speed

• the faster the clock, the greater number of instructions the CPU can execute
• the system will run faster and smoother as a result

USB

Also known as Universal Serial Bus.

• the industry standard for connections between personal computers and their peripheral devices
• such connects consist of:
  • cables
  • connectors and protocols for connection
  • communication
  • power supply

Fetch-execute

Also known as the instruction cycle, is a cycle depicting the basic operation of a computer system.

• consists of 4 stages:
  • fetch
  • decode
  • execute
  • store (usually omitted)

Registers used

• PC - program counter
• IR - (current) instruction register
• MDR - memory data register
• MAR - memory address register

Fetch

1. CPU sends contents inside PC to MAR and reads the command on the address bus
2. memory returns the data stored at the memory location indicated by PC on the data bus
3. CPU copies the data from the data bus into its MDR
4. CPU copies the data from the MDR to IR for instruction decoding
5. PC points to the next instruction

Decode

• decoding happens in the CU
• allows CPU to determine:
  • what instruction is to be performed
  • what operands need to be fetched to perform this instruction

Execute

• the function of the instruction is performed
  • if the instruction involves arithmetic or logic, the ALU is called for

Register transfer notation

• describes the operations performed by registers
• uses the abbreviation of registers
  • e.g: MAR, PC, IR etc.

Representing the fetch stage

• MAR ← [PC]
• PC ← [PC] + 1; MDR ← [ [MAR] ]
• IR ← [MDR]

Details of the notation

MAR ← [PC]

• the format for individual data transfer is similar to variable assignment
  • the first item written is the destination of the data

Simultaneous operations

PC ← [PC] + 1; MDR ← [[MAR]]

• this means that the two transfers occur simultaneously
• the operations are separated by a semicolon

Square brackets

MAR ← [PC]

MDR ← [[MAR]]

• MAR - the register storing the address
• [MAR] - the stored address
• [[MAR]] - the data at that stored address

Interrupts

A signal to the processor emitted by hardware or software indicating an event that needs immediate attention.

• stops the processors current job
• allow the system to appear to 'multitask'
• each interrupt needs to be handled appropriately
• different interrupts may have different priorities

Causes of interrupts

• a fatal error in a program
• a hardware fault
• a need for I/O processing to begin
• user interaction
• a timer signal

Interrupt register

• a hardware register in a computer chip used to configure the chip to generate interrupts

Interrupt handler / ISR

Also known as Interrupt Service Routine.

• a software process that is called by an interrupt request
• stops any processes (programs) currently running and sends the interrupt request to the CPU

Steps of ISR

1. interrupt received
2. finishes current fetch-execute cycle
3. contents inside all registers stored
4. source of interrupt identified
   • if low priority, then disable
   • if high priority, PC loaded with address of appropriate ISR
5. ISR executed
6. all registers, except for PC, are restored
7. interrupts reenabled
8. PC content restored

Scenarios where ISR is used

• computer processes will continue running until interrupted
  • if a key on a keyboard is pressed, an interrupt signal is sent
  • CPU is then called to process this input

Instruction sets

A complete set of all the instructions in machine code that can be recognised and executed by the CPU.

Categories

• data movement (register to main memory and vice versa)
  • modes of addressing: immediate, direct, indirect, indexed, relative
• input and output of data
• arithmetic operations
  • compare instructions
• unconditional and conditional jump instructions

Data movement

Sets a register to a value, copies data from a memory location to a register or read/writes from a hardware device.

STO <address>

• stores the contents of ACC at the given address

Modes of addressing

LDM #n

Immediate addressing.

• loads the number #n to ACC

LDD <address>

Direct addressing.

• loads the contents at <address> to ACC

LDI <address>

Indirect addressing.

• uses the address stored at <address>

LDX <address>

Indexed addressing.

• forms the address by adding <address> to the contents of the index register.
• copies the content of this calculated address to ACC

Relative addressing

• locates the new address by adding or subtracting values from a reference address

Input and output data

IN

• keys in a character and stores its ASCII value in ACC

OUT

• outputs the ASCII value's corresponding character stored in ACC

Arithmetic operations

Performs mathematical calculations.

ADD <address>

• adds the contents of <address> to the ACC

INC <register>

• add 1 to the contents of <register> (either ACC or IX)

DEC <register>

• subtract 1 from the contents of <register> (either ACC or IX)

Compare instructions

Compares two registers to see whether one is greater than, less than or equal to one another.

CMP <address> or #n

• compares the contents of ACC with the contents of <address>
• compares the contents of ACC with number #n

Unconditional / conditional jump

Jump (or branch) to a specified instruction. Can optionally depend on conditions of TRUE or FALSE.

JMP <address>

• jump to <address>

JPE <address>

• used after a compare (CMP) instruction
• jump to <address> if the compare was TRUE

JPN <address>

• used after a compare (CMP) instruction
• jump to <address> if the compare was FALSE

Other

END

• returns control to the operating system

Assembly language

• a low level programming language that resembles the architecture of machine code
• a higher tier than machine code

Machine code

• a low level programming language consisting of binary or hexadecimal instructions
• the computer (CPU) can understand and execute directly

Relationship between Assembly language and Machine code

Similarities

• assembly language contains the same instructions as a machine language

Differences

• assembly instructions / variables use names
• machine code uses just numbers.

Symbolic address

MOTOR_ON

• uses names or symbols to assign an address
• easier to read

Absolute address

FB21

• uses the literal ID or value of the address
  • e.g: the memory location

Directives

A language construct (word syntax).

• specifies how a compiler (or other translator) should process an input

Macros

Also known as macroinstructions.

• a programmable pattern which turns a sequence of inputs into a sequence of outputs

Two-pass assembler

This type of assembler scans over the source code twice; hence 'two-pass'.

• progresses through the assembly code line by line
• machine code is generated for each line

Why use two-pass assemblers?

• if a jump instruction is scanned and the location to be jumped is further down, the assembler will have guess the location
  • this would result in incorrect code

• to avoid guessing, the assembler scans once and records any jumps and locations
• the second scan then generates the respective code for each instruction