About me

I am a semiconductor professional and researcher with over 14 years of industrial experience in layout design engineering, currently employed as a Senior Staff Engineer in the semiconductor industry. I earned my B.Tech. in Electronics and Communication Engineering and M.Tech. in VLSI Design from the Indian Institute of Technology (IIT) Roorkee, where I am presently pursuing a Ph.D. in the area of compact device modeling.

My professional background encompasses extensive work in deep submicron and FinFET process technologies, focusing on analog, digital, and mixed-signal layout design, design rule optimization, and layout-dependent effects. This industrial experience provides me with a strong practical foundation in device-layout interactions and physical verification challenges across advanced technology nodes.

In my doctoral research, I am primarily engaged in physics-based compact modeling of advanced semiconductor devices, with particular emphasis on carrier transport mechanisms, short-channel effects, and variability modeling for emerging device architectures. My research aims to establish accurate, scalable, and computationally efficient compact models suitable for circuit simulation and design optimization.

Broadly, my academic and professional pursuits lie at the intersection of device physics and modeling, driven by a passion for advancing the predictive accuracy and physical interpretability of next-generation semiconductor device models.