1. ¿Cuál es el objetivo de cada uno de esos proyectos con sus palabras y describa que debe hacer para desarrollarlo?
El objetivo de esta practica es construir los chips que se describen en la unidad numero 3, utilizando compuertas primitivas y chips que se han visto en capítulos previos. Se hará uso del simulador para poder alcanzar el objetivo de esta practica.
Objetivo:
Construir los chips que se describen en el capítulo 2 hasta construir la unidad lógica aritmética del computador (ALU).
Tareas a realizar:
Construir el HalfAdder y FullAdder.
Aumentar la funcionalidad de Add16 y Inc16.
Construir el ALU.
CHIP HalfAdder {
IN a, b; // 1-bit inputs
OUT sum, // Right bit of a + b
carry; // Left bit of a + b
PARTS:
// Put you code here:
And(a=a, b=b, out=carry);
Xor(a=a, b=b, out=sum);
}
CHIP FullAdder {
IN a, b, c; // 1-bit inputs
OUT sum, // Right bit of a + b + c
carry; // Left bit of a + b + c
PARTS:
// Put you code here:
Xor(a=a, b=b, out=xor1);
Xor(a=xor1, b=c, out=sum);
And(a=xor1, b=c, out=or1);
And(a=a, b=b, out=or2);
Or(a=or1,b=or2, out=carry);
}
CHIP Add16 {
IN a[16], b[16];
OUT out[16];
PARTS:
// Put you code here:
HalfAdder(a=a[0], b=b[0], sum=out[0], carry=c0);
FullAdder(a=a[1], b=b[1], c=c0, sum=out[1], carry=c1);
FullAdder(a=a[2], b=b[2], c=c1, sum=out[2], carry=c2);
FullAdder(a=a[3], b=b[3], c=c2, sum=out[3], carry=c3);
FullAdder(a=a[4], b=b[4], c=c3, sum=out[4], carry=c4);
FullAdder(a=a[5], b=b[5], c=c4, sum=out[5], carry=c5);
FullAdder(a=a[6], b=b[6], c=c5, sum=out[6], carry=c6);
FullAdder(a=a[7], b=b[7], c=c6, sum=out[7], carry=c7);
FullAdder(a=a[8], b=b[8], c=c7, sum=out[8], carry=c8);
FullAdder(a=a[9], b=b[9], c=c8, sum=out[9], carry=c9);
FullAdder(a=a[10], b=b[10], c=c9, sum=out[10], carry=c10);
FullAdder(a=a[11], b=b[11], c=c10, sum=out[11], carry=c11);
FullAdder(a=a[12], b=b[12], c=c11, sum=out[12], carry=c12);
FullAdder(a=a[13], b=b[13], c=c12, sum=out[13], carry=c13);
FullAdder(a=a[14], b=b[14], c=c13, sum=out[14], carry=c14);
FullAdder(a=a[15], b=b[15], c=c14, sum=out[15], carry=c15);
}
CHIP Inc16 {
IN in[16];
OUT out[16];
PARTS:
// Put you code here:
Add16(a=in, b[0]=true,b[1..15]=false, out=out);
}
CHIP ALU {
IN
x[16], y[16], // 16-bit inputs
zx, // zero the x input?
nx, // negate the x input?
zy, // zero the y input?
ny, // negate the y input?
f, // compute out = x + y (if 1) or x & y (if 0)
no; // negate the out output?
OUT
out[16], // 16-bit output
zr, // 1 if (out == 0), 0 otherwise
ng; // 1 if (out < 0), 0 otherwise
PARTS:
Mux16(a=x, sel=zx, out=x1);
Not16(in=x1, out=negatedX);
Mux16(a=x1, b=negatedX, sel=nx, out=x2);
Mux16(a=y, sel=zy, out=y1);
Not16(in=y1, out=negatedY);
Mux16(a=y1, b=negatedY, sel=ny, out=y2);
Add16(a=x2, b=y2, out=added);
And16(a=x2, b=y2, out=xyAnd);
Mux16(a=xyAnd, b=added, sel=f, out=result);
Not16(in=result, out=negatedResult);
Mux16(a=result, b=negatedResult, sel=no, out=out, out[15]=firstOut, out[0..7]=finalLeft, out[8..15]=finalRight);
// output == 0 (zr)
Or8Way(in=finalLeft, out=zrl);
Or8Way(in=finalRight, out=zrr);
Or(a=zrl, b=zrr, out=nzr);
Not(in=nzr, out=zr);
And(a=firstOut, b=true, out=ng);
}
Objetivo:
Construir los chips que se describen en el capítulo 3 hasta construir la memoria de acceso aleatorio (RAM).
La DFF primitiva permite programar un registro como un flipflop D activado por flanco.
Consta de una entradas y dos salidas.
Entrada: in.
Salidas: out, out.
El "flip-flop" tipo D, sigue a la entrada y realiza transiciones que coinciden con las de la entrada. El término "D", significa dato; este "flip-flop" almacena el valor que está en la línea de datos. Se puede considerar como una celda básica de memoria. Un "flip-flop" D, se puede hacer con un "flip-flop" "set/reset", uniendo la salida set (estado alto) con la salida reset (estado bajo), a través de un inversor. El resultado se puede sincronizar.
CHIP Bit {
IN in, load;
OUT out;
PARTS:
// Put your code here:
Mux(a=out1, b=in, sel=load, out=r);
DFF(in=r, out=out1, out=out);
}
CHIP Register {
IN in[16], load;
OUT out[16];
PARTS:
// Put your code here:
Bit(in=in[0], load=load, out=out[0]);
Bit(in=in[1], load=load, out=out[1]);
Bit(in=in[2], load=load, out=out[2]);
Bit(in=in[3], load=load, out=out[3]);
Bit(in=in[4], load=load, out=out[4]);
Bit(in=in[5], load=load, out=out[5]);
Bit(in=in[6], load=load, out=out[6]);
Bit(in=in[7], load=load, out=out[7]);
Bit(in=in[8], load=load, out=out[8]);
Bit(in=in[9], load=load, out=out[9]);
Bit(in=in[10], load=load, out=out[10]);
Bit(in=in[11], load=load, out=out[11]);
Bit(in=in[12], load=load, out=out[12]);
Bit(in=in[13], load=load, out=out[13]);
Bit(in=in[14], load=load, out=out[14]);
Bit(in=in[15], load=load, out=out[15]);
}
CHIP RAM8 {
IN in[16], load, address[3];
OUT out[16];
PARTS:
// Put your code here:
DMux8Way(in=true, sel=address, a=a, b=b, c=register3, d=register4, e=register5, f=register6, g=register7, h=register8);
And(a=a, b=load, out=load0);
And(a=b, b=load, out=load1);
And(a=c, b=load, out=load2);
And(a=d, b=load, out=load3);
And(a=e, b=load, out=load3);
And(a=f, b=load, out=load4);
And(a=g, b=load, out=load5);
And(a=h, b=load, out=load6);
Mux8Way16(a=R0, b=R1, c=R2, d=R3, e=R4, f=R5, g=R6, h=R7, sel=address, out=out);
}
CHIP RAM64 {
IN in[16], load, address[6];
OUT out[16];
PARTS:
// Put your code here:
DMux8Way(in=load, sel=address[0..2], a=A, b=B, c=C, d=D, e=E, f=F, g=G, h=H);
RAM8(in=in, load=A, address=address[3..5], out=outa);
RAM8(in=in, load=B, address=address[3..5], out=outb);
RAM8(in=in, load=C, address=address[3..5], out=outc);
RAM8(in=in, load=D, address=address[3..5], out=outd);
RAM8(in=in, load=E, address=address[3..5], out=oute);
RAM8(in=in, load=F, address=address[3..5], out=outf);
RAM8(in=in, load=G, address=address[3..5], out=outg);
RAM8(in=in, load=H, address=address[3..5], out=outh);
Mux8Way16(a=outa, b=outb, c=outc, d=outd, e=oute, f=outf, g=outg, h=outh, sel=address[0..2], out=out);
}
CHIP RAM512 {
IN in[16], load, address[9];
OUT out[16];
PARTS:
// Put your code here:
DMux8Way(in=load,sel=address[0..2],a=register1,b=register2,c=register3,d=register4,e=register5,f=register6,
g=register7,h=register8);
RAM64(in=in,load=register1,address=address[3..8],out=out1);
RAM64(in=in,load=register2,address=address[3..8],out=out2);
RAM64(in=in,load=register3,address=address[3..8],out=out3);
RAM64(in=in,load=register4,address=address[3..8],out=out4);
RAM64(in=in,load=register5,address=address[3..8],out=out5);
RAM64(in=in,load=register6,address=address[3..8],out=out6);
RAM64(in=in,load=register7,address=address[3..8],out=out7);
RAM64(in=in,load=register8,address=address[3..8],out=out8);
Mux8Way16(a=out1,b=out2,c=out3,d=out4,e=out5,f=out6,g=out7,h=out8,sel=address[0..2],out=out);
}
CHIP RAM4K {
IN in[16], load, address[12];
OUT out[16];
PARTS:
// Put your code here:
DMux8Way(in=load, sel=address[0..2], a=A, b=B, c=C, d=D, e=E, f=F, g=G, h=H);
RAM512(in=in, load=A, address=address[0..8], out=outa);
RAM512(in=in, load=B, address=address[0..8], out=outb);
RAM512(in=in, load=C, address=address[0..8], out=outc);
RAM512(in=in, load=D, address=address[0..8], out=outd);
RAM512(in=in, load=E, address=address[0..8], out=oute);
RAM512(in=in, load=F, address=address[0..8], out=outf);
RAM512(in=in, load=G, address=address[0..8], out=outg);
RAM512(in=in, load=H, address=address[0..8], out=outh);
Mux8Way16(a=outa, b=outb, c=outc, d=outd, e=oute, f=outf, g=outg, h=outh, sel=address[0..2], out=out);
}
CHIP RAM16K {
IN in[16], load, address[14];
OUT out[16];
PARTS:
// Put your code here:
DMux4Way(in=load,sel=address[0..1],a=register1,b=register2,c=register3,d=register4);
RAM4K(in=in,load=register1,address=address[2..13],out=out1);
RAM4K(in=in,load=register2,address=address[2..13],out=out2);
RAM4K(in=in,load=register3,address=address[2..13],out=out3);
RAM4K(in=in,load=register4,address=address[2..13],out=out4);
Mux4Way16(a=out1,b=out2,c=out3,d=out4,sel=address[0..1],out=out);
}
CHIP PC {
IN in[16],load,inc,reset;
OUT out[16];
PARTS:
// Put your code here:
Mux16(a=out1,b[0..15] = false, sel= reset, out=out4);
Mux16(a=out3, b=in, sel=load, out=out1);
Mux16(a=outf, b=out2, sel=inc, out=out3);
Inc16(in=outf,out=out2);
Register(in=sal3,load=true,out=out,out=ent);
}
Video explicativo sobre el producto final de la practica numero 3, donde se explica todo lo relacionado con la misma.
BIBLIOGRAFIA.
Schocken, S. and Nisan, N., 2021. NAND2Tetris - Project 01. [online] NAND2Tetris. Disponible en: https://www.nand2tetris.org/project01
Nisan, N., & Schocken, S. (2005). The Elements Of Computing Systems. Disponible en: The Elements of Computing Systems: Building a Modern Computer from First Principles (uis.edu.co)
Alvarez, J. E. (s. f.). vrExperienceStudio. Recuperado 15 de noviembre de 2021, de http://allsensexperience.com/trabajos_en_desarrollo/controladores/project_01.html