Workshop on Architecting Error Corrected Quantum Computers (ARQTEC) is a venue to share ideas to build next-generation fault-tolerant quantum computers that are free from boiling errors. Quantum computers have shown potentials to transform the landscace of computing in a broad ranges of applications, including but not limited to drug discovery, financial modeling, weather forecasting. To achieve quantum supremacy, refraining from noises is mandatory. ARQTEC has the mission to cross the knowledge boundaries of design stacks and faciliate the realization of truely error corrected quantum computers. ARQTEC targets to uncover new paths to transit from the current NISQ era to future fault-tolerant era.
Rapid progress in scaling quantum hardware has generated significant excitement in academia and Industry. However, to truly unleash the quantum advantage, fault-tolerant quantum computing is essential, and Quantum Error Correction (QEC) can pave this path toward fault tolerance. Decade-long work in QEC theory has yielded a variety of quantum codes, with a recent highlight on quantum low-density parity-check (qLDPC) code. Despite the advancement on the theory side, real-world deployment is challenging. So far, only small-scale experiments on a few qubits have been demonstrated. There is a significant gap between what is attainable now and what is anticipated in the future. To that end, this ARQTEC workshop has the mission to share ideas about quantum error correction from algorithm, circuit, architecture, and compiler perspectives and beyond, as well as how to enable the transition from the NISQ era to a fault-tolerant era. This workshop encourages cross-stack thinking towards performant, efficient, automated, scalable, distributed quantum error correction and the synergy among different techniques for fault-tolerant quantum computing. This workshop welcomes global pioneering researchers to share their perspectives on quantum error correction and fault-tolerant quantum computing to advance quantum computing.
Quantum error correction code design and encoding techniques
Decoding algorithm/architecture/software/system integration/simulation
Syndrome extraction circuit/hardware design and optimization
Resource estimation for quantum error correction
Theory and simulation for logical qubit operation.
Any other techniques towards fault-tolerant quantum computing
Format:
Submissions can be either work-in-progress research papers or positioning papers.
Submissions must be printable PDF files. Format should follow HPCA submission requirements: double-column; single-space; English text; Times font; at minimum 10 pt font size; up to 6 pages, including references.
The review process will follow double-blind review process, and submissions shall not include any author identifying information.
Accepted papers will be presented at the workshop and included in the workshop report.
Important Dates:
Submission deadline: Jan 23, 2025 (AOE) Feb 7, 2025 (AOE)
Acceptance notification: Feb 15, 2025
Camera ready: Feb 25, 2025
Workshop: Mar 2, 2025
Submission site: https://arqtec2025.hotcrp.com/
Contact: di.wu@ucf.edu; swamit@cs.wisc.edu