To view last year's workshop page, please visit ARCHIDE2024.
The demand for specialized architectures and innovative approaches is growing to sustain performance and enhance energy efficiency in the post-Moore era of high-performance and scientific edge computing. In the realm of scientific instruments and HPC systems, the development of custom and specialized accelerators -- such as those based on ASICs, FPGAs, and other custom or reconfigurable architectures -- is crucial not only for advancing scientific discoveries but also for meeting efficiency goals. This workshop focuses on architectural designs for HPC and scientific instruments, along with related technologies, methodologies, and tools. We aim to explore topics and opportunities in innovative architectural approaches, hardware design languages, simulation, emulation, verification methodologies and tools, chip prototyping, emerging accelerators and architectures, compiler stacks, programming paradigms, and relevant application areas -- with particular emphasis on energy-efficient computing solutions. Participants will present their recent work in these fields. The workshop also offers opportunities to share knowledge, techniques, tools, and source code related to hardware specialization, encouraging an open and practical dialogue. Additionally, we aim to foster collaborative discussions aligned with DOE/MEXT collaborations.
The topics of interests include but are not limited to:
Open-source hardware tool ecosystems
Chisel, Firesim, Verilator, cocotb, OpenRoad, Chipyard, MoSAIC, etc.
Custom hardware designs (ASIC, FPGA)
HPC/AI accelerator designs
near-detector data processing hardware designs for X-ray science, high-energy physics, quantum computing, etc
compression, deep neural network, spiking neural network
surface codes for quantum computing error correction
tight-integration with AI accelerators such as Groq
5G acceleration designs
Common research testbeds/resources and source-code repositories
Chameleon cloud, an experimental testbed for computer science, for example
Discussions about collaborations
future events/workshop
potential roadblocks such as NDA, licenses, resources
Organizers: Kazutomo Yoshii (ANL), Kentaro Sano (RIKEN), John Shalf (LBNL), Jeff Vetter (ORNL), Rajesh Sankaran (ANL)