Approximate Systolic Arrays

This website is part of paper "Design and Evaluation of Inexact Computation based Systolic Array for Convolution" in LasCAS 2023.

Systolic Array (SA) architecture is a unique computation architecture where the inputs are continuously flowing, and the processing elements perform the desired computations in parallel. SA’s are prominently investigated due to the emergence of heavy and large processing elements for modern-day Convolution Neural Network (CNN) applications. Taking this cue, SA architectures of the order of kernel size and configured with approximate multipliers are investigated for image processing applications. The approximate array multiplier derived from approximate 4-2 compressors were employed to achieve hardware benefits without losing on the image quality metrics. The SA architecture is configured to the same size as filter kernels in a view to achieve maximum utilization, and the same is compared with other existing SA architectures for hardware metrics. The computational time for processing an image of size 256 × 256 was evaluated for approximated SA. This work investigates approximate SA for Gaussian smoothening and image outline feature extraction applications to showcase the reliability of the design. The novel approximate SA architecture is a step toward designing compact sized SoC designs for real-time image and video processing applications.

We use the systolic arrays of sizes 3x3, 5x5 and 7x7 with both approximate and exact multiplier based PE. Gaussian Smoothning and image outlining is performed on the image.

Resources :

https://en.wikipedia.org/wiki/Systolic_array

https://sites.google.com/view/approxmul/home