Approximate Multipliers

This site is part of paper "Design and Evaluation of In-Exact Compressor based Approximate Multipliers" . https://dl.acm.org/doi/10.1145/3526241.3530320

Verilog Source files for all the multiplier designs used in the paper :

The top modules are in top_1step.v, top_2step.v and top_3step.v

To use the multipliers, instantiate the required multiplier top module in your application, and add the other verilog files in project.

Source code

Testbench to obtain the simulation results, and perform error analysis as discussed in paper :

Testbench

Following slides help to understand the compressors design :

WebsitePresentation

Please note : The mapping for naming in paper to this website

One-Step-Ap --> 1step

One-Step-Ap-Logic-Pruning --> 1step_trunc

Two-Step-Ap --> 2step

Two-Step-Ap-Logic-Pruning --> 2step_trunc

Three-Step-Ap --> 3_step

Three-Step-Ap-Logic_pruning --> 3step_trunc

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