First name: Anh | Last name: Nguyen (Ms.)
Researcher at ICT Systems Laboratory, Fujitsu Ltd.
PhD in Information and Communications Engineering,
Tokyo Institute of Technology
Email: anh.nguyen at fujitsu.com
Google scholar: https://scholar.google.com/citations?user=TNNA1RYAAAAJ&hl=en
High performance computing
Reconfigurable architectures
High-Level Synthesis
SAT solver
Internet of Things
Reconfigurable architectures
Sep 2018 - Sep 2021: Ph.D. degree in Information and Communications Engineering, Tokyo Institute of Technology, Japan
Also enrolled at the Academy for Global Leadership, Tokyo Institute of Technology
Thesis topic: Amoeba-Inspired SAT Solver for IoT Edge Devices
This work aims at realizing a Satisfiability problem (SAT) solver, AmoebaSAT, whose algorithm was inspired from a single cell amoeba, on resource-constrained IoT edge devices. As the solver possesses a massive parallelism feature where processing elements perform computations in parallel to decide variable assignments, we conducted its FPGA-based hardware implementations using a high-level design approach. Based on the original AmoebaSAT solver, we extended the algorithm to help the solver escape from local minima more quickly and achieved significant speedup to outperform state-of-the-art hardware SAT solvers. Moreover, by utilizing the inter-variable dependency feature of different SAT instances, we achieved further iteration reduction without incurring effects on hardware usage.
Sep 2016 -Sep 2018: Master Degree in Information and Communications Engineering, Tokyo Institute of Technology, Japan
Thesis topic: High-level Synthesis of Amoeba-inspired SAT Solvers on FPGA
The Amoeba-inspired SAT (satisfiability) algorithm bases on a computing model inspired from the behavior of an amoeba (a single cell organism) in its adaption with the surrounding environment. This computing model, AmoebaSAT, can effectively solve SAT problems, which can be extended to understand various combinatorial optimization problems that appear in many practical applications, especially IoT applications. This work aims at realizing an efficient hardware AmoebaSAT solver on an FPGA, through exploring several hardware implementations by high level synthesis (HLS).
Sep 2011 - Sep 2016: Bachelor Degree in Electronics and Telecommunications, Hanoi University of Science and Technology, Vietnam (top 5% students)
Thesis topic: Level of Traffic Service Classification System
Traffic Level of Service (LOS) information is crucial for traffic management systems, especially in urban areas. This work proposes a cost effective distributed traffic estimation solution using smart cameras, each of which is equipped with a low cost ARM microprocessor to estimate the LOS from the captured traffic images.
Received Japanese Government (MEXT) Scholarship from September 2016 - September 2021
Received AmCham scholarship from the American Chamber of Commerce in Vietnam in 2015
Received Vietnam's Outstanding Technical Female Student Award in 2015 (Selected by Center for Vietnam Youth Talents, Science and Technology)
Received Encouragement Scholarship for Excellent Study Records in HUST for 5 semesters
Nov 2021 -present: Fujitsu Research, Fujitsu Ltd.
Nov 2023 - present: Assigned Researcher at Fujitsu Co-creation Laboratory, Fujitsu Canada.
Nov 2021 - Oct 2023: Researcher at Computing Laboratory, Fujitsu Ltd.
Oct 2024: Principal researcher
Apr 2024: Senior researcher
Dec 2020 - Mar 2021: Research intern with Assoc. Prof. Christian Pilato, Polytechnico di Milano
Aug - Sep 2020: Research intern at Preferred Networks Japan | Chip Hardware Team
2017 - Sep 2021: Teaching assistant at Online Education Development Office, Tokyo Institute of Technology
I worked on the preparation of several MOOC/EdX online courses organized by Tokyo Tech, mainly on video shooting and editing.
Jul - Aug 2015: Intern at Toshiba Japan | Embedded systems position, System & Software Solution Center