RESEARCH

Ph.D. Topic: Investigating Probabilistic Computing: Devices, Circuits, and Systems

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University: Indraprastha Institute of Information Technology Delhi (IIIT-Delhi)

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Supervisor: Dr. Sneh Saurabh

Collaborator: Dr. Ram Krishna Ghosh

Year: 2018 to 2025

Journal Papers:

• • Amina Haroon and Sneh Saurabh, "Fault-Tolerant Design Framework for Probabilistic-Bit (P-Bit) Systems: Proposal and Analysis" in IEEE Transactions on Circuits and Systems I: Regular Papers (Impact Factor 5.2)

Abstract: Probabilistic-bit (p-bit) systems are promising computational platforms due to their potential for high energy efficiency, particularly when implemented using stochastic elements like low energy-barrier nanomagnets that exploit inherent thermal stochasticity. However, these stochastic elements are susceptible to getting stuck to a given state or transitioning too slowly due to faults arising during fabrication, ageing or other operational issues. This paper examines the impact of such faults on p-bit systems using a subset of the MNIST handwritten dataset as a case study and shows degraded system functionality due to such faults. To address these challenges, we propose a methodology based on mutual information to evaluate the criticality of individual p-bits in a network for a given application, quantifying their influence on system accuracy. Using the proposed criticality score (CS), we identify the most impactful p-bits and employ them in guiding fault-tolerance strategies. Additionally, we introduce the design of testable p-bits to detect faults in critical p-bits, validated through SPICE simulations using 14nm HP-FinFET technology. To further enhance fault resilience, we propose isolatable and fault-tolerant p-bits that help tackle accuracy loss caused by stuck-at faults. While these designs incur area overhead due to additional transistors, we can use the criticality score to replace only the most essential p-bits with fault-tolerant p-bits, minimizing unnecessary overhead while achieving desired fault-tolerance levels. Thus, this work demonstrates a comprehensive framework to develop fault-tolerance capabilities in a p-bit system implemented using stochastic elements susceptible to stuck-at faults. 

• • Amina Haroon, Ram Krishna Ghosh, and Sneh Saurabh, "Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis" in IEEE Transactions on Circuits and Systems I: Regular Papers (Impact Factor 5.2)

Abstract: Probabilistic computing is a promising computational paradigm that harnesses the inherent stochasticity of devices to tackle problems that can benefit from stochastic-driven search. A probabilistic bit (p-bit), the workhorse of probabilistic computing, is popularly implemented using energy-efficient low-barrier nanomagnets, highly-scaled transistors, and unstable memory elements. These implementations are prone to process-and environmental-induced variations and aging-induced non-idealities. These non-idealities can manifest as unwanted bias in a p-bit and its incoming signals, impacting the figures of merit of probabilistic computing. For the first time, this work systematically investigates this aspect of probabilistic computing. First, we investigate the behavior of a non-ideal p-bit using an analytical model proposed in this work and corroborate the results using numerical computation. Then, we examine the impact of these non-idealities on the functionality and robustness of the probabilistic computing using Boolean logic implementation and image completion networks in the forward and backward modes of operation, respectively. For Boolean logic implementation, the weight matrix is found to be robust enough to allow p-bit network to retain its intended functionality despite non-idealities. Moreover, we show that there can be canceling effects of non-idealities, which can potentially be utilized in compensating reliability-induced degradation in a p-bit network. Additionally, using 1T-1MTJ-based p-bit implementation and SPICE simulations, we illustrate the applicability of the proposed model in analyzing and assessing the impact of non-idealities and process-induced variations on a p-bit network. We also demonstrate that statistical analysis techniques, such as Monte Carlo simulations, can help derive application-dependent constraints on the non-ideality of p-bits. These constraints will serve as critical design criteria for future p-bit implementations. 

Conferences/Workshops:

• Amina Haroon, Ram Krishna Ghosh, and Sneh Saurabh, "Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and Analysis", in 36th International Conference on VLSI Design (VLSID) 2023 , Oct. 2022

Abstract: Probabilistic spin logic (PSL) is a recently proposed computational paradigm targeting a specific class of problems. Earlier works show the better performance of PSL compared to digital computation in terms of speed and energy efficiency for a few optimization problems such as traveling salesman problem (TSP), max-cut problem, etc. PSL is implemented using probabilistic bits or pbits that fluctuate randomly between two metastable states. One of the popular methods of realizing a pbit is a 3T-1MTJ implementation, with a low barrier magnet (LBM) acting as the free layer of the magnetic tunnel junction (MTJ). In this paper, we perform extensive simulations to examine the suitability of LBMs for 3T-1MTJ pbit implementation. We have analyzed the impact of various material parameters on the attributes of a pbit. Further,  we propose a method of selecting material parameters for an LBM-based pbit implementation that improves flips per second (fps), a crucial system-level figure of merit (FOM), without sacrificing the ideal sigmoid-type output response.

• Amina Haroon and Sneh Saurabh, "Image Completion using a Sparse Probabilistic Spin Logic Network", in 35th International Conference on VLSI Design (VLSID) 2022 , Jan. 2022

Abstract: Probabilistic Spin Logic (PSL) is a recently proposed computational paradigm implemented using unstable stochastic units called probabilistic bits, or pbits. The stochastic nature of the pbits is responsible for its unique invertibility property. In this paper, we have exploited the invertibility property to complete a partial image. The digit image set consists of ten images of digits 0 to 9 of size 5 X 3 pixels for training the PSL network. Results show that the fully connected PSL (FC-PSL) network successfully recovers the unclamped pixels for all the digits. Moreover, we propose an area-efficient sparsely connected PSL (SC-PSL) network with ~ 42% of the original connections. First, we perform the sparsification on an FC-PSL network using the conventional weight pruning methods. Next, we propose a method to predict the  SC-PSL network structure using mutual information based on the perspective of information theory.

Teaching Assistant (Aug. 2018 to Oct. 2024):

• VLSI Design Flow: RTL to GDS (NPTEL) (Jul. 2024 - Oct. 2024)

     Instructor: Dr. Sneh Saurabh, ECE Department, IIIT Delhi

• VLSI Design Flow: RTL to GDS (NPTEL) (Jul. 2023 - Oct. 2023)

     Instructor: Dr. Sneh Saurabh, ECE Department, IIIT Delhi

• ECE-111 - Digital Circuits (Jul. 2019 - Dec. 2019)

          Instructor: Dr. Sneh Saurabh, ECE Department, IIIT Delhi

• ECE-214 - Integrated Electronics (Jan. 2019 - Jun. 2019)

          Instructor: Dr. Sujay Deb, ECE Department, IIIT Delhi

• ECE-215 - Circuit Theory and Devices (Jul. 2018 - Dec. 2018)

          Instructor: Dr. Shobha Sundar Ram, ECE Department, IIIT Delhi

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Click here to access my Resume (Last Updated September 2025)