Journals

2019-2021

• • Dong-Jin Chang, Byeong-Gyu Nam, and Seung-Tak Ryu, “MixedNet: A Network Design Strategies for Cost-effective Quantized Convolutional Neural Network”, IEEE Acess, vol.9, pp. 117554-117564, 2021.

  • Dong-Jin Chang, Michael Choi, and Seung-Tak Ryu, “A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-ranging SAR ADC with On-Chip Background Skew Calibration,” IEEE Journal of Solid-State Circuits,  vol. 56, no. 9, pp. 2691-2700, Sep. 2021. 

  • Dong-Jin Chang, Byeong-Gyu Nam, and Seung-Tak Ryu, “Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron”, IEEE Trans. on Circuits and Syst. I: Regular papers,  vol. 67, no. 12, pp. 5189-5199, Dec. 2020.

  • Yi-Ju Roh, Dong-Jin Chang, and Seung-Tak Ryu, “A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC with Double Clock-Rate Coarse Decision”, IEEE Trans. on Circuits and Syst. II: Express Briefs, vol. 67, no. 12, pp. 2833-2837, Dec. 2020.

2015-2019

• Min-Jae Seo, Yi-Ju Roh, Dong-Jin Chang, Wan Kim, Ye-Dam Kim, and Seung-Tak Ryu, “A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks”, IEEE Trans. on Circuits and Syst. II: Express Briefs,  vol. 65, no. 12, pp.1904-1908, Apr. 2018.

• Dong-Jin Chang, Min-Jae Seo, Hyeok-Ki Hong, and Seung-Tak Ryu, “A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration”, IEEE Trans. on Circuits and Syst. II: Express Briefs,  vol. 65, no. 3, pp. 281-285, Mar. 2018.

• Dong-Ryeol. Oh, Jong-In. Kim, Dong-Shin. Jo, Woo-Chul Kim, Dong-Jin Chang, and Seung-Tak Ryu, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration”, IEEE Journal of Solid-State Circuits, vol. 54, no. pp. 288-297, Oct. 2018. 

• Dong-Jin Chang, Wan Kim, Min-Jae Seo, Hyeok-Ki Hong, and Seung-Tak Ryu, “Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC”, IEEE Trans. on Circuits and Syst. I: Regular papers,  vol. 64, no. 2, pp. 322-332, Jan. 2017.

• Wan Kim, Hyeok-Ki Hong, Yi-Ju Roh, Hyun-Wook Kang, Sun-Il Hwang, Dong-Shin Jo, Dong-Jin Chang, Min-Jae Seo, and Seung-Tak Ryu, “A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC”, IEEE Journal of Solid-State Circuits, vol. 54, no. pp. 1826-1839, Jun. 2016.