2025~
H. -K. Hong, J. Kang, B. Jung, N. Koo, S.-J. Kim, H. Lee, D.-J. Chang, M. Kim, J. Suh, J. Kim, T. Lee, A. Ju, J. Lee, C.-W Shin, K. Park, and C. Bae, "A 1024-Channel VCO-Based CTDSM Neural Readout IC with Slot-Level Channel Replacement," in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2025, pp. 259-261, doi: 10.1109/A-SSCC67472.2025.11349417.
~2022
Dong-Jin Chang and Seung-Tak Ryu, "A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs," 2022 IEEE Symp. on VLSI Technology and Circuits (S. VLSI Technology and Circuits), Honolulu, HI, USA, 2022, pp. 174-175.
Seung-Yong Lim, Raymond Mabilangan, Dong-Jin Chang, Young-Jae Cho, Michael Choi, and Seung-Tak Ryu, "An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation," in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2021, pp. 1-3.
Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Dong-Jin Chang and Seung-Tak Ryu, "A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization," in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2021, pp. 1-3.
Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Dong-Jin Chang, Won-Mook Lim, Jae-Hyun Chung, Eun-Ji An, and Seung-Tak Ryu, “A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability”, in Proc. IEEE Asian Solid State Circuit Conf. (A-SSCC), Nov. 2019, pp. 189-192.