RTL DESIGN AND DESIGN VERIFICATION

INDEPENDENT STUDY ON UVM TESTBENCH FOR AMBA AXI BASED SOC

• Implementing UVM test bench to verify the functionality of SoC consisting of AMBA AXI4 interconnect, ALU and JPEG blocks
• Implementing block level environments for the fabric, ALU and JPEG subsystems and simulating the test bench in QuestaSim
• Implementing chip level environment for the interconnect, ALU and JPEG subsystems and ensure 100% functional coverage

UVM TESTBENCH FOR LC3 MICROCONTROLLER

• Implemented UVM test bench to verify the functionality of 5 stages of data path of the LC3 microcontroller
• Implemented block level environment for the 5 stages and the data & instruction memory operations and simulated the test bench in QuestaSim
• Emulated the setup in Veloce Emulator. Created test plan and achieved 100% coverage. Identified the 30 bugs in the design

FUNCTIONAL VERIFICATION OF LC3 MICROCONTROLLER

• Implemented a re-usable layered test bench to verify the functionality of 5 stages of data path, and control path of the LC3 microcontroller
• Designed Driver and Monitor inside the Agent to drive the pseudo-random instruction into DUT through interface
• Designed scoreboard and predictor model to verify all stages and obtained 100% coverage using SystemVerilog Assertions and cover bins

Hardware Implementation of Convolutional Neural Network

• Implemented a synthesizable hardware accelerator of two-stage convolutional neural network algorithm on a 12*12 input grid using FSM
• The design achieved minimum area and maximum clock frequency by simultaneous use of multiple MAC modules from Synopsys Designware
• Meeting time constraints, fully operational functionality was synthesized with Performance per unit area = 1.541 s^-1um^-2

MICRO-ARCH/ PERFORMANCE MODELING

Superscalar out-of-order processor simulator

• Developed simulator for out-of-order Superscalar Processor with stages: Fetch, Issue, Execute, Write Result & Commit
• The processor works on Tomasulo’s Algorithm and dynamically schedules and issues up to 4 instructions per cycle
• Reorder Buffer was integrated into the architecture

Cycle-accurate 5 stage pipelined MIPS simulator

• Developed a pipelined MIPS simulator processor which supports integer & floating point instruction
• Implemented in-order issue and out-of-order execution
• Handled control, structural, data hazards and included latency of L+1 cycles in the design

Cache Simulator

• Developed a two-level (L1 and L2) n-way set associative cache hierarchy simulator, with Victim Cache and replacement policy- LRU and LFU and write policies: Write-Back Write-Allocate, Write-Through Write Not-Allocate
• Developed trace-driven simulator for handling coherence in 4-processor parallel architecture
• Simulated MSI, MESI, MOSI and MOESI protocols on individual L1 caches of four processors