Dr. Akashdeep Saha

 I am a postdoctoral associate at the Design For Excellence (DfX) Lab with Prof. Ozgur Sinanoglu at NYUAD. Currently, I am working on integrating LLMs into hardware security specifically in circuit analysis and logic locking. Prior to joining NYUAD, I defended my PhD in August 2024. I worked under the supervision of Prof. Debdeep Mukhopadhyay and Prof. Rajat Subhra Chakraborty at the SEAL, Department of CSE, IIT Kharagpur.

My research primarily focused on the systematic design and efficient automated implementation of secure Logic Locking. During my PhD, I successfully devised attacks on purportedly secure and advanced logic locking techniques for both combinational and sequential circuits, enabling the extraction of all secret information from locked circuits. Subsequently, I developed countermeasures to mitigate a variety of existing attacks on logic locking. A significant contribution of my work is the utilization of the security robustness of cryptographic SPN-based block ciphers such as PRESENT and GIFT in the design of logic locking, providing long-term security guarantees. Additionally, I developed an end-to-end framework for automating combinational logic locking across all genres of combinational logic.

In one of my research endeavors, I explored theoretical aspects of Indistinguishability Obfuscation (iO) and proposed practical iO constructions. Furthermore, I designed a novel error correction code configuration aimed at minimizing entropy leakages, thereby reducing the number of PUF response bits required to generate secret keys in fuzzy extractors and incurring lesser overheads.

I greatly appreciate the following organizations for their generous fellowship support during my PhD

•  DRDO, India

•  Intel Labs, India & Santa Clara 

•  Winner of the best poster award at SPACE Conference 2021.

• Recipient of DAC Young Fellows program grant for full-conference registration to attend the 57th DAC in San Francisco, 2020.

• Second position in the “Embedded Security Challenge” as part of the Cyber Security Awareness Week 2018 (CSAW 2018).

• Recipient of full tuition fee waiver for Bachelor of Technology (B. Tech) in CSE course.

• INSPIRE Scholarship of INR 4,00,000 by virtue of performance within the top 1% in India in ISC examination 2014.

• First place in the school in ISC 2014 (12th standard).

• Second place in the school in ICSE 2012 (10th standard).

• T. Sarkar, S. Maitra, A. Chakraborty, A. Saha, J. Chowdhury, and D. Mukhopadhyay, “X-Factor: Utilizing X-Ray Microscopy for Printed Circuit Board Analysis”, 2024 ACM 9th International Workshop on Malicious Software and Hardware in Internet of Things, Italy, 2024. [MAL-IoT 2024]

• A. Saha, S. Chowdhury, R. S. Chakraborty, and D. Mukhopadhyay, “MIDAS: an End-to-end CAD Framework for Automating Combinational Logic Locking”, under submission, major revision, T-IFS, 2023.

• P. B. Roy, J. Knechtel, A. Saha, S. Sreekumar, L. Mankali, M. Nabeel, D. Mukhopadhyay, R. Karri, and Ozgur Sinanoglu, “NiLoPher: Breaking a Modern SAT-Hardened Logic Locking Scheme via Power Analysis Attack”, Cryptology ePrint Archive, Paper 2024/309, https://eprint.iacr.org/2024/309, 2024.

• A. Saha, H. Banerjee, R. S. Chakraborty, and D. Mukhopadhyay, “Revisiting Logic Obfuscation Using Cellular Automata (Invited Paper)”, Proceedings of First Asian Symposium on Cellular Automata Technology, Chapter No. 3, pp. 27-41, Springer, 2022. [ASCAT 2022]

• A. Saha, U. Chatterjee, D. Mukhopadhyay, and R. S. Chakraborty, “DIP Learning on CASLock: Using Distinguishing Input Patterns for Attacking Logic Locking”, 2021 IEEE Design, Automation & Test in Europe Conference & Exhibition, 2022, pp. 688-693. [DATE 2022]

• A. Saha, D. Mukhopadhyay, and R. S. Chakraborty, “Design and Analysis of Logic Locking Techniques”, 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration, 2021 Oct. 4, pp. 1-2. [VLSI-SoC 2021]

• A. Saha, H. Banerjee, R. S. Chakraborty, and D. Mukhopadhyay, “ORACALL: An Oracle Based Attack on Cellular Automata Guided Logic Locking”, IEEE Tran. on ComputerAided Design of Integrated Circuits and Systems, 40(12), pp.2445-2454. [TCAD 2021]

• A. Saha, S. Saha, S. Chowdhury, D. Mukhopadhyay, and B. B. Bhattacharya, “LoPher: SAT Hardened Logic Embedding on Block Ciphers”, 2020 57th ACM/IEEE Design Automation Conference, San Francisco, CA, USA, 2020, pp. 1-6. [DAC 2020]

• D. Mukhopadhyay, R. S. Chakraborty, A. Saha, S. Das, “Automated CAD Framework for Logic Obfuscation”, filed Indian patent, 2023,               Application number 202331039318, dated 08-06-2023.

• Reviewer of Journals: IEEE TCAD, IEEE TIFS, IEEE TVLSI, ACM TECS, ACM JETC, IACR TCHES, Springer Sãdhanã

• Reviewer of Conferences: DAC, DATE, HOST, ICCAD, SPACE, VLSI-SoC, Asian HOST, CCS, ASHES, USENIX

• Organization of National and International Events:

– International Conference on Security, Privacy and Applied Cryptographic Engineering (SPACE) at Indian Institute of Technology,     Kharagpur, India, December 2021.

– Workshop on Cyber Physical System Security, Indian Institute of Technology, Kharagpur, India, December 2019.

– Workshop on Advanced Side Channel Evaluation of Hardware Security, Indian Institute of Technology, Kharagpur, India, July 2018.

I am passionate about football and enjoy traveling and capturing moments through photography.

Contact: akashdeepsaha[ninetyfive] [at] gmail [dot] com