Domain: Physical Design, FPGA Design, STA, Signoff checks, Low power circuit design, CMOS and beyond CMOS : CNTFET, FinFET Technology based circuit design and analysis.
EDA Tools: -
Synopsys Design Compiler, ICC2 : Floorplan, Powerplan, Placement, CTS, Routing - Signoff - StarRC, IC Validator, Primetime STA
Simulation Tools ng-Spice, H-spice - Mentor Graphics: S-edit, L-edit; - Microwind, DSCH 3.9
NI MultiSim 14.1, MATLAB R2021a, Proteus, Eagle, easyEDA
Hardware: FPGA Spartan 6,Vertex,Zynq board, PIC Microcontroller, Arduino , Raspberry Pi, PLC FX 5U
Xilinx ISE 14.1,Vivado 2016.4 (Synthesis and analysis of HDL Designs)
RTL2GDS using OpenLANE
Machine Learning and Artificial intelligence algorithms
Programming Language/scripting: C, C++, Core Java, Python,Javascript , TCL
“Design of stable and efficient novel 13T differential SRAM cell” , Journal CHIP, https://doi.org/10.1016/j.chip.2025.100171
“Design of Stable 10T FinFET SRAM Cell for Operation in Sub-Threshold Regime”, SSRG International Journal of Electrical and Electronics Engineering, vol. 12, no. 6, pp. 206-213, 2025
“Design and implementation of secure cryptographic algorithms for wireless sensor networks in healthcare applications”, Journal of Discrete Mathematical Sciences and Cryptography,2025
“Design and Stability Optimization of 6T FinFET SRAM Cell using Strategic Multi-Fin Configuration”, Proceedings 2025 5th International Conference on Expert Clouds and Applications Icoeca 2025
“A Deep Learning Approach to Track Real-Time Objects Using YOLO and DeepSORT for Next-Gen Security and Surveillance”, 2025 6th International Conference on Data Intelligence and Cognitive Informatics Icdici 2025
“Static Noise Margin Evaluation of Planar CMOS and FinFET based Static Random Access Memory for Nanoscaled Technology” 5th International Conference on Recent Trends in Computer Science and Technology (ICRTCST)- 2024.
“Investigating the Impact of Technology Scaling on Stability Performance of Sub-threshold Static Random Access Memory Bitcell Topologies”, Journal of Electrical Systems, 2024
“Stability and Power Analysis of Schmitt Trigger based low power SRAM bitcell using CMOS and CNTFET technology at 22nm technology node”, 11th international conference on nanostructures, nanomaterials and nanoengineering, Tokyo,Japan,November 26-28, 2022
"The Stability Performance Analysis of SRAM Cell Topologies in 90nm and 130nm CMOS technology," 2021 International Conference on Emerging Smart Computing and Informatics (ESCI), (IEEE Xplore) 2021, pp. 733-736, doi: 10.1109/ESCI50559.2021.9396973.
Driver Assistance System Using Image Processing And Deep Learning Algorithm , International Journal For Technological Research In Engineering, Volume 7, Issue 10, June-2020, ISSN (Online): 2347 – 4718
Machine Learning Approach for Crop Yield Improvement using Plant Leaf Disease Detection”, International Research Journal of Engineering and Technology (IRJET) Volume 7, Issue 4, April 2020 S.NO: 936
“Object Detection and Recognition for Blind Assistance”, International Research Journal of Engineering and Technology (IRJET), Volume: 06 Issue: 05 | May 2019, p-ISSN: 2395-0072, e-ISSN: 2395-0056.
“Chemical Mixing for Process Industry Using PLC & SCADA” International journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol.7, Issue 4, April 2018
“Read stability and read failure analysis of low voltage Schmitt Trigger based SRAM bit cell,” International Journal of Engineering Research and Applications, Vol. 3, Issue 1, January -February 2013, pp.876-879.
“Read stability and Write ability analysis of different SRAM cell structures,” International Journal of Engineering Research and Applications Vol. 3, Issue 1, January -February 2013, pp.1073-1078.
Patents
Cognitive Cleaning Mechanism for Solar Panel/s, Application Number-202221028430, 18/05/2022 (INDIA)(Granted).
Flexible road divider Application Number - 202221032275,06/06/2022 (INDIA) (Granted).
Fire Extinguishing system with hose controlling mechanism and method thereof, Application Number - 202521053566 June 2025 (Published).
A System and method for automated structural health assessment of brick Application Number – 202421045852, June 2024, (Published).
A system and method for flood alert, Application Number-202421045867, June 2024, (Published)
Device and method for extracting music present in a digital content,Application Number 202421043873, June 2024, (Published)
Design of Design Of Novel Differential 13T Sram Cell For Improved Read And Write Performance with integrated Lower Control Technique In Subthreshold Region” Indian Patent, Application no. 202521074790. (Filed).
Reconfigurable Architecture for Autism Detection (RAAD), Aug 2021.(Australia)
Pure Water analysis using near field technology and internet of things, Aug 2021.(Australia)
Copyrights
Technology scaling impact on behavioral performance analysis of Static RAM, 2023
Design of static random access memory using advanced FET technology in nanometer regime, 2023.
Lab manual of Mechatronics, 2018
System programming and operating system laboratory manual, 2018
Pureflow: Smart water quality monitoring and contamination detection system 2025
Projects
VLSI, Low Power and Physical Design Projects:
CHIPTOP : Block Level Physical Design, (2022) Technology -16nm CMOS process Node, macros-04, Metal Layers:09
Falcon: Block Level Physical Design, (2022) Technology -22nm CMOS process Node, macros-16, , Metal Layers:09
JBI: Synthesis, PNR and STA of the block, (2022) Technology -16nm, Macros: 46, Metal Layers:09
DTMF: Block Level Physical Design, (2022) Technology -22nm CMOS process Node, macros-16, , Metal Layers:09
Stability and Speed performance analysis of CMOS and FinFET based 10T SRAM bit-cell topology in 90nm, 7 Months (2019)
10 bit DAC Design using esim and sky130 (2022)
Technology Scaling Impact on Behavioral performance analysis of Static RAM. (2023)
Reviewer in Web of Science SCIE Journal – Microelectronics International
Reviewer for Third International Conference on Computing, Communication, Control and Automation 2017, track VLSI Embedded Systems organized by Pimpri Chinchwad College of Engineering & Technically Sponsored by IEEE Pune Section.
Reviewer for fifth International Conference on Computing, Communication, Control and Automation 2019, track Automation Syatems organized by Pimpri Chinchwad College of Engineering & Technically Sponsored by IEEE Pune Section.
Seminar on ‘IPR – Application and process’ at PES’s Modern College of Engineering, Shivaji Nagar, Pune on 8th June 2017.
Deliver lecture on “Insights on Patent Filing” at Electronics and Telecommunication Department PES’s Modern College of Engineering, Pune on 23rd Feb 2018.
Deliver guest lecture on “ Patent Awareness and its commercialization aspect” at IT Dept. PCCOE, Nigdi
Deliver guest lecture on “Turning idea into IP” at PG (E&Tc) Dept. PCCOE Nigdi.
IEEE Nanotechnology Council, IEEE Council on Electronic Design Automation
ISRD(International Society for Research and Development)
InSC ( Institute of Scholars)
Industrial Trainings and Internships
Physical Design Training | VLSI For All |( Jan –May 2023) 6 Months
Physical Design Training | Chipedge Technologies Pvt Ltd Bangalore ( August 2022- Dec 2022) – Duration 4 Months
Analog system design and simulation using cadence virtuoso | BharatIC ( Dec 2024 Feb 2025) – Duration 2 Months
Training on PLC Automation at Innovative Solutions India Pvt. Ltd., in 2020, with a duration of 1 week.
“Innovative VLSI Physical Design using Innovus” organised by department of cognitive computing,SIMATS school of engineering, SIMATS,Thandalam,Chennai, 9 January 2023-13 January 2023.
“Advanced physical design using openlane/sky130”, 3rd -7th August 2022, cloud based workshop conducted by VLSI system design.
“FinFET, Nano-Sheet cell design , Now & Road Ahead” ; An educational perspective by 'Dr. Etienne Sicard', Tool: Microwind, Date : September 14 to 16, 2022
“Design and Simulation of Low Power Integrated Circuits using H-spice tool at Deep Submicron Technology” at PCETS PCCoE Pune-44 (2016)
“Full Custom ASIC Design and Verification using Mentor graphics Tanner tool” organized by Sandeepani School of Embedded System Design , Bangalore, 26-28 May 2021
Internship at Entuple Technologies Pvt. Ltd (17th August 2021- 23rd Sept 2021) : Training on Physical Design flow , Concepts in Floorplanning, Powerplanning,Placement, Clock Tree synthesis, Routing, Innovus Implementation System –Cadence tool is used for performing Physical design activities placement, optimization, routing and clocking,STA Analysis, Multi-mode Multi-corner (MMMC) analysis is performed using Cadence Tempus
Internship at Technogeek IT Solutions Pune – (Sept 2019-Jan 2020), Project: Implementation of Naive Bayes based machine learning model for a chemical industry to take actions on leakages of Hazardous gas. Development of machine learning model in Python; Performed Data processing using libraries Numpy, Pandas and Data visualization using Seaborn and matplotlib.
MOOC Course Details with E-certifications
Successfully completed Innovation Ambassador Training – Foundation Level, conducted by AICTE, Ministry of Education, Government of India, in June 2021, comprising 16 sessions (30 hours) during 30/06/2021 – 30/07/2021.
Successfully completed Course on Research and Publication Ethics (2 Credit), conducted by Savitribai Phule Pune University (SPPU), during 26/12/2023 – 25/01/2024.
FDP / Workshop Attended
Participated in EDGE AI Workflow Design, organized by IEEE SPS Pune Chapter, in July 2024.
Participated in VLSI Design: IC to Silicon, organized by SIEM (Sandip Foundation), Nashik, in July 2024.
Participated in NEP 2020 Orientation and Sensitization FDP, organized by UGC, in February 2024.
Attended High End Workshop on Emerging Nanomaterial Based Devices for Future VLSI Applications, conducted under DST-SERB, in December 2022.
Attended Applied Machine Learning Using Python, organized by IETE & IEEE Pune Section, in September 2020.
Participated in Mechatronics Lab Experiments with Virtual Kits – An Initiative for Innovative Teaching Learning Methods, organized by PICT Pune, in October 2020.
Attended Faculty Orientation Workshop on Electronic Skill Development, organized by SPPU, in June 2020.
Attended SoC Design Using Open Source EDA Tools, organized by MeitY, Government of India, in February 2020.
Attended FDP on Mechatronics, organized by Savitribai Phule Pune University (SPPU), in June 2017.
Participated in Faculty Orientation Workshop on System Programming and Operating System, conducted by SPPU, in December 2017.
Attended Development of Mechatronics Systems Using Arduino – A Project Based Learning Approach, organized by IET Pune Chapter, in August 2017.
Participated in Faculty Orientation Workshop on Object Oriented Programming, conducted by SPPU, in December 2016.
Attended Design and Simulation of Low Power Integrated Circuits Using H-Spice at Deep Submicron Technology, conducted under AICTE-QIP, in February 2016.
Google Scholar Link
https://scholar.google.com/citations?user=ASTDpbwAAAAJ&hl=en&authuser=2
Scopus Profile Link
https://www.scopus.com/authid/detail.uri?authorId=57223044641
LinkedIn Link
https://www.linkedin.com/in/ajjay-gaadhe-1402871b/