CECE 209: Digital Logic Design (II)

An introduction to advanced topics of Digital Logic Design such as latches, flip-flops, design of sequential circuits, shift registers, counters, etc.

Topics

A tentative schedule of the topics is as follows:

Chapter 7: Latches, Flip-Flops, and Timers
Chapter 8: Shift Registers
Chapter 9: Counters
Chapter 11: Data Storage

Grading

Your final grade will be computed from the following components:

Participation 5pt

Assignments 15pt

Project 5pt

Midterm Exam 15pt

Final Exam 60pt

Total Points 100pt

Attendance

You are expected to attend all classes. If you miss a class, you are responsible for getting the notes and any verbal information given during class from a fellow classmate.

Assignments

Assignments are graded not just on correctness (producing the correct output) — neatness counts. Here neatness means that your Assignment is well formatted and nicely presented.

If you cannot complete an assignment, you should still submit what you attempted. Partial credit will be given for reasonable effort. Late work will not be accepted.

You will be submitting your assignments to the teaching assistant.

Academic Integrity

We assume that any classwork (homework, project, etc) you submit is created by your own individual effort (or by group members’ efforts if groups are allowed).

Note that receiving help from your instructor or the teaching assistant does not violate this academic integrity policy.

Students who violate this academic integrity policy will receive a grade of 0 for that assignment. A second violation will also result in a reduction of 10pts from the student's grade. In the case where one student copies the program of another student, both students are considered to have violated this policy.

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