Speakers

David Patterson

Title: A New Golden Age for Computer Architecture

Abstract: In the 1980s, Mead and Conway democratized chip design and high-level language programming surpassed assembly language programming, which made instruction set advances viable. Innovations like Reduced Instruction Set Computers (RISC), superscalar, and speculation ushered in a Golden Age of computer architecture, when performance doubled every 18 months. The ending of Dennard Scaling and Moore’s Law crippled this path; microprocessor performance improved only 3% last year! The ending of Dennard scaling and Moore's law and the deceleration of performance gains for standard microprocessors are not problems that must be solved but facts that if accepted offer breathtaking opportunities. We believe high-level, domain-specific languages and architectures, freeing architects from the chains of proprietary instruction sets and the demand from the public for improved security will usher in a new Golden Age. Aided by open source ecosystems, agilely developed chips will convincingly demonstrate advances and thereby accelerate commercial adoption. The instruction set philosophy of the general-purpose processors in these chips will likely be RISC, which has stood the test of time. We envision the same rapid improvement as in the last Golden Age, but this time in cost, energy, and security as well as in performance. Like in the 1980's, the next decade will be exciting for computer architects in academia and in industry!

Bio: David Patterson is a professor emeritus of Computer Science at UC Berkeley, a distinguished engineer at Google, and Vice-Chair of the Board of Directors of the RISC-V Foundation. He received his BA, MS, and PhD degrees from UCLA. His most successful research projects were likely Reduced Instruction Set Computer (RISC), Redundant Array of Inexpensive Disks (RAID), and Network of Workstation (NOW). All three projects helped lead to multibillion-dollar industries. This research led to many papers and seven books, with the best known being Computer Architecture: A Quantitative Approach co-authored by John Hennessy, now in its sixth edition. His most recent book is The RISC-V Reader: An Open Architecture Atlas, co-authored by Andrew Waterman. Patterson is a member of the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. His teaching was honored with the ACM Karlstrom Award and the IEEE Mulligan Medal. As a past president of ACM and a past Chair of CRA, he received Distinguished Service Awards from ACM, CRA, and SIGARCH and the Tapia Achievement Award for Scientific Scholarship, Civic Science, and Diversifying Computing. His most recent award is the ACM A.M Turing Award, shared with John Hennessy, which is the highest award in computer science.

Vivienne Sze

Title: Domain-Specific Architectures for AI and Robotics: Opportunities and Challenges

Abstract: In this talk, we will describe the key computational kernels for emerging applications such as artificial intelligence (AI) and robotics. These applications often require a significant amount of computation and involve processing and manipulating high-dimensional data, which make it difficult to meet the energy efficiency, high throughput, and/or low latency demands. We will highlight various opportunities that are afforded by domain-specific architectures to address these challenges. For instance, domain-specific architectures can exploit certain properties of the workload, such as parallelism and data-access patterns, to efficiently deliver data to the processing engine. Domain-specific architectures also allow for the co-design of algorithms and architectures to open the design space; for instance, algorithms can be made to be more hardware-friendly and change the workloads that the hardware needs to support. We will also discuss the various challenges for domain-specific architectures, for instance, the need to balance flexibility with efficiency.

Bio: Vivienne Sze is an Associate Professor at MIT in the Electrical Engineering and Computer Science Department. Her research interests include energy-aware signal processing algorithms, and low-power circuit and system design for portable multimedia applications, including computer vision, deep learning, autonomous navigation, and video process/coding. Prior to joining MIT, she was a Member of Technical Staff in the R&D Center at TI, where she designed low-power algorithms and architectures for video coding. She also represented TI in the JCT-VC committee of ITU-T and ISO/IEC standards body during the development of High Efficiency Video Coding (HEVC), which received a Primetime Engineering Emmy Award. She is a co-editor of the book entitled “High Efficiency Video Coding (HEVC): Algorithms and Architectures” (Springer, 2014).

Prof. Sze received the B.A.Sc. degree from the University of Toronto in 2004, and the S.M. and Ph.D. degree from MIT in 2006 and 2010, respectively. In 2011, she received the Jin-Au Kong Outstanding Doctoral Thesis Prize in Electrical Engineering at MIT. She is a recipient of the 2019 Edgerton Faculty Award, the 2018 Facebook Faculty Award, the 2018 & 2017 Qualcomm Faculty Award, the 2018 & 2016 Google Faculty Research Award, the 2016 AFOSR Young Investigator Research Program (YIP) Award, the 2016 3M Non-Tenured Faculty Award, the 2014 DARPA Young Faculty Award, the 2007 DAC/ISSCC Student Design Contest Award, and a co-recipient of the 2017 CICC Outstanding Invited Paper Award, the 2016 IEEE Micro Top Picks Award and the 2008 A-SSCC Outstanding Design Award.

For more information about research in the Energy-Efficient Multimedia Systems Group at MIT visit: http://www.rle.mit.edu/eems/

Serge Leef

Title: Automatic Implementation of Secure Silicon

Abstract: Throughout the past decade, cybersecurity threats have evolved from attacks focused high in the software stack to progressively lower levels of computational hierarchy. With the explosion of popularity and growing deployment of internet connected devices, economic attackers and nation-states alike are shifting their attention to Application Specific Integrated Circuits (ASICs) that enable complex capabilities across commercial and military application domains. Despite growing recognition of the problem and a substantial body of research across multiple chip security areas, no common tools, methods or solutions are in wide use today. Modern synchronous digital ASICs are already very complex and expensive to design and incorporation of security is viewed as a burden with unclear economic benefits. The result is that the majority of today’s ASICs are largely unprotected. Absence of automation makes incorporation of security a laborious, manual task that generally requires very specific design expertise not generally possessed by semiconductor companies. These dynamics can be altered with a novel chip design flow that aims to protect advanced ASICs from known attack strategies by streamlining inclusion of scalable defense mechanisms into an automated process that maximizes architectural exploration of security vs. economics trade-offs while improving design productivity. The effort and cost to incorporate a level of hardware security aligned with application requirements and economics will be significantly reduced so that incorporation of security at all levels of hardware design is feasible and affordable.

Bio: Mr. Serge Leef joined DARPA in August 2018 as a program manager in the Microsystems Technology Office (MTO). His research interests include computer architecture, simulation, synthesis, semiconductor intellectual property (IP), cyber-physical modeling, distributed systems, secure design flows, and supply chain management. He is also interested in the facilitation of startup ecosystems and business aspects of technology.

Leef came to DARPA from Mentor, a Siemens Business where from 2010 until 2018 he was a Vice President of New Ventures, responsible for identifying and developing technology and business opportunities in systems-oriented markets. Additionally, from 1999 to 2018, he served as a division General Manager, responsible for defining strategies and building successful businesses around design automation products in the areas of hardware/software co-design, multi-physics simulation, IP integration, SoC optimization, design data management, automotive/aerospace networking, cloud-based electronic design, Internet of Things (IoT) infrastructure, and hardware cybersecurity.

Prior to joining Mentor, he was responsible for design automation at Silicon Graphics, where he and his team created revolutionary, high-speed simulation tools to enable the design of high-speed 3D graphics chips, which defined the state-of-the-art in visualization, imaging, gaming, and special effects for a decade. Prior to that, he managed a CAE/CAD organization at Microchip and developed functional and physical design and verification tools for major 8- and 16-bit microcontroller and microprocessor programs at Intel.

Leef received his Bachelor of Science degree in electrical engineering and Master of Science degree in computer science from Arizona State University. He has served on corporate, state, and academic advisory boards, delivered numerous public speeches, and holds two patents.

Andrew Kahng

Title: Bringing Design Technology and Architecture Closer Together: What Open Source Might Enable

Abstract: Computer architects are always among the first to embrace prospective new hardware technology: Every question can be asked/answered afresh when a new device, interconnect, memory, or integration technology appears on the horizon. It is natural to ask whether the methods used to answer microarchitecture/system design questions have kept pace with combinatorial possibilities (beyond-Moore, beyond-CMOS, beyond-von Neumann …) and exploding system complexities. For example, between architecture and technology models, “the hardware design process” is a strong determinant of power, performance, cost, etc. outcomes seen in final hardware implementations.

An ongoing U.S. DARPA project, OpenROAD (“Foundations and Realization of Open, Accessible Design”), seeks to develop open-source electronic design automation tools for 24-hour, “no-human-in-the-loop” hardware layout generation. The project applies machine learning, distributed/parallel optimization, and other fundamental elements toward the goal of an autonomous hardware (layout) generation process. Today’s talk will explore whether open-source design technology (along with its underlying methods, such as machine learning and distributed search) can potentially “reboot” the relationship between computer architects and design technologists.

Bio: Andrew B. Kahng is Professor of CSE and ECE and holder of the endowed chair in high-performance computing at UC San Diego. He was visiting scientist at Cadence (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 400 journal and conference papers, holds 34 issued U.S. patents, and is a fellow of ACM and IEEE. He served as general chair of DAC, ISPD and other conferences, and from 2000-2016 as international chair/co-chair of the ITRS Design and System Drivers working groups. He is currently PI of “OpenROAD”, an $11.3M U.S. DARPA project targeting open-source, autonomous (“no humans”) tools for IC implementation

Yungang Bao

Title: The Four Steps to An Open-Source Chip Design Ecosystem

Abstract: The open-source software ecosystem has made tremendous contributions to the flourishing Internet era. Today, small teams are able to develop a mobile app in just a few months through open-source based agile software development. However, the barrier of chip design is still very high in terms of time and cost. As people are envisioning how an open-source chip design ecosystem will change the traditional way in which we build chips, in this talk, I will present the four essential steps towards that goal. We will also share our practices and efforts on these steps, especially in the research and education areas.

Bio: Yungang Bao is a Professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the director of Center of Advanced Computer Systems (ACS) of ICT. He received B.S. degree from Nanjing University in 2003 and his Ph.D. degree from ICT in 2008 and was a post-doctoral researcher at Princeton University during 2010-2012. His research interests include computer architecture and systems and serves on program committees of ASPLOS, ISCA, MICRO and SC etc. His research work such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache (absorbed and implemented in Intel's DDIO technology) and PARSEC 3.0 has been adopted by industry including Alibaba, Huawei, Intel, and the research community. He was the youngest plenary keynote speaker at China National Computer Congress (CNCC) in 2016 and was invited to give a keynote presentation at ARM Research Summit 2018. He was the winner of CCF-Intel Young Faculty Award of the year for 2013. He received Outstanding Award of Youth Innovation Promotion Association, Chinese Academy of Sciences in 2017 and won China's National Lofty Honor for Youth under 40 in 2019.

Richard Ho

Title: Building a sustainable open source hardware ecosystem

Abstract: The open source hardware community is a faint shadow of the open source software community. Closed source intellectual property pervades EDA tools, subsystem IP and cores. The CHIPS Alliance is a new organization of industry, academia and exceptional individuals who aim to show that an open source hardware community can be built on the principles of active collaboration, high quality contributions, permissive licensing and nurturing the entire hardware ecosystem. In this talk, the goals and principles of the CHIPS Alliance will be discussed and current progress described.

Bio: Richard received his Ph.D. in Computer Science from Stanford University. He was a co-founder of 0-In Design Automation and an early technologist involved with assertions, formal property verification and CDC verification. Richard was also part of the team that built the Anton and Anton2 supercomputers for molecular dynamics simulation at D. E. Shaw Research. He is currently part of the datacenter chip team at Google working on TPU and other cool projects.

Mark Horowitz

Title: AHA! – Agile HArdware

Abstract: VLSI design needs to change. To counter the reduced gains from technology scaling, computer architects have turned to application-tuned accelerators to scale computing performance. But the current design approaches need time to study the application space, architect the hardware accelerator, and then map the application to the accelerator: a waterfall approach to design, which leads to slow design cycles and large NRE costs. Software moved away from this design approach decades ago. People point to the high cost and long processing time needed for silicon fabricate to justify their waterfall approach.

This talks points out the fallacy of this argument. First, agile design is mostly about reuse, leveraging existing tools and code to complete your system as quickly as possible. This requires effort on creating clean interfaces, refactoring systems when these interfaces break down, and building meta-level components (templates or domain specific languages) to allow more reuse. Second, the hardware fabrication cycle time doesn’t need to be in the critical path of the innovation loop. We show how to using a malleable hardware substrate allows one to rapidly iterate on an end-to end system design, allowing the hardware substrate to “evolve” into an application accelerator. We will show one example of how to apply these ideas to hardware/software system design. We are working to create such a system for visual computing applications.

Bio: Mark Horowitz is the Yahoo! Founders Professor at Stanford University and was chair of the Electrical Engineering Department from 2008 to 2012. He co-founded Rambus, Inc. in 1990 and is a fellow of the IEEE and the ACM and a member of the National Academy of Engineering and the American Academy of Arts and Science. Dr. Horowitz's research interests are quite broad and span using EE and CS analysis methods to problems in molecular biology to creating new design methodologies for analog and digital VLSI circuits.

Jason Cong

Title: Democratize Customizable Computing

Abstract: With large-scale deployment of FPGAs in both private and public clouds in the past two years, customizable computing is going from advanced research into mainstream computing.

Although the performance and energy efficiency benefits of customizable computing have been clearly demonstrated, a significant challenges, however, is the efficient design and implementation of various accelerators on FPGAs. It presents a significant barrier to many software programmers, despite the recent advance in high-level synthesis. In this talk, I shall present our recent research on source-code level transformation and optimization for customizable computing, including support of high-level domain-specific languages (DSL) for deep learning (e.g. Caffe), imaging processing (e.g. Halide), and big-data processing (e.g. Spark), and suppoort automated compilation to customized microarchictecture templates, such as systolic arrays, stencils, and CPPs (composable parallel and pipelined).

Bio: Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Distinguished Chancellor’s Professor at the Computer Science Department, also with joint appointment from the Electrical Engineering Department, of University of California, Los Angeles, the director of Center for Domain-Specific Computing (CDSC), and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. He served as the chair the UCLA Computer Science Department from 2005 to 2008. Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and highly scalable algorithms. He has close to 500 publications in these areas, including 13 best paper awards, three 10-Year Most Influential Paper Awards, and the first paper inducted to the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPGAs (renamed to Vivado HLS after Xilinx’s acquisition). He was elected to an IEEE Fellow in 2000, ACM Fellow in 2008, and the National Academy of Engineering in 2017.

Brucek Khailany

Title: Machine-Learning-Assisted Agile VLSI Design for Machine Learning

Abstract: As we reach the end of Moore’s law, hardware designers are now confronted with the reality of needing to increase chip capabilities without the benefit of exploiting lower-cost transistors each product generation. Application-specific hardware accelerators for key workloads (e.g. machine learning inference) provide an opportunity to increase capability by improving performance or energy efficiency compared to general-purpose processors, but historically, design productivity has limited their adoption and time-to-market. To address this challenge, we propose to use better VLSI design automation techniques to lower these design productivity barriers. In this talk, we will highlight two design automation research directions being pursued in the ASIC and VLSI Research group at NVIDIA: (1) An automated C++-to-layout VLSI flow that leverages high-level synthesis (HLS) tools and open-source HLS-compatible C++ libraries for design productivity; and (2) Machine-learning assisted VLSI design techniques. We will also describe our experience using these tools as part of an agile hardware design flow to build for a deep neural network (DNN) inference accelerator testchip consisting of 36 small chips connected in a mesh network on a multi-chip-module (MCM). Each 6 mm² chip was implemented in 16nm technology and achieves 1.29 TOPS/mm², 0.11 pJ/op energy efficiency, 4 TOPS (8b int) peak performance on 1 chip, and 128 peak TOPS and 2,615 images/s ResNet-50 inference in a 36-chip MCM.

Bio: Brucek Khailany joined NVIDIA in 2009 and currently leads the ASIC & VLSI Research group. He leads research efforts into innovative design methodologies for rapid chip development, ML-assisted and GPU-assisted EDA algorithms, and energy-efficient accelerator architectures for machine learning. During his time at NVIDIA, he has contributed to projects within both research and product groups on topics spanning computer architecture, unit micro-architecture, and ASIC and VLSI design techniques. Previously, Dr. Khailany was a Co-Founder and Principal Architect at Stream Processors, Inc. (SPI) where he led research and development activities related to highly-parallel programmable processor architectures. He received his Ph.D. and Masters in Electrical Engineering from Stanford University and received B.S.E. degrees in Electrical Engineering and Computer Engineering from the University of Michigan.

Borivoje Nikolić

Title: Generating the Next Wave of Custom Chips

Abstract: The emerging wave of computing does not have one clear product that drives the industry; rather, a diversity of emerging applications are based on the interaction between edge devices and the cloud. Supporting differentiation amongst diverse products requires specialization of integrated circuits, which in turn requires a paradigm shift in the design of custom chips. This talk outlines a vision of dramatic increase in design reuse by developing digital and mixed-signal generators rather than specific instances of functional modules. The use of the open and extensible RISC-V instruction-set architecture enables customization with reduced software cost. Open-source chip generators amortize the design and verification costs across many instances. Mixed-signal blocks are generated as well, to enable generation of complete systems on chip (SoCs). Several examples of generated SoCs will be presented.

Bio: Borivoje Nikolić holds the National Semiconductor Distinguished Professorship in the Department of EECS of the University of California, Berkeley. He received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Serbia respectively in 1992 & 1994, and the Ph.D. degree from the University of California at Davis in 1999. For work with his students and colleagues he has received the best paper awards at the IEEE International Solid-State Circuits Conference, Symposium on VLSI Circuits, IEEE International SOI Conference, European Solid-State Device Research Conference, European Solid-State Circuits Conference, S3S Conference and the ACM/IEEE International Symposium of Low-Power Electronics.

Adam Chlipala

Title: Strong Formal Verification Across a Hardware-Software Stack with RISC-V

Abstract: In the 20th century, academic researchers in formal methods have typically done formal verification against the actual source code of software but only models of hardware systems, because realistic hardware has been IP-encumbered. One exciting thing about RISC-V is the chance to build new hardware and apply formal-proof methods to synthesizable descriptions, where the hardware is nonetheless compatible with very well-developed software toolchains and SoC infrastructure. I will summarize research of this kind at MIT, where we are implementing and proving complete RISC-V-based systems, at first for simple Internet-of-things applications, using no legacy code feeding into hardware RTL or software machine code, writing machine-checked proofs that relate the stack holistically to specifications of interaction with the environment. These sorts of proofs involve a variety of engineering challenges, including modularization, to let us analyze each component independently.

Bio: Adam Chlipala has been on the faculty in computer science at MIT since 2011. He did his undergrad at Carnegie Mellon and his PhD at Berkeley, and his research focuses on clean-slate redesign of computer-systems infrastructure, typically taking advantage of machine-checked proofs of functional correctness. Much of his work uses the Coq proof assistant, about which he has written a popular book, "Certified Programming with Dependent Types." He most enjoys finding opportunities for drastic simplification over incumbent abstractions in computer systems, and some favorite tools toward that end are object-capability systems, transactions, proof-carrying code, and high-level languages with whole-program optimizing compilers. Some projects particularly far along the real-world-adoption curve are Fiat Cryptography, for proof-producing generation of low-level cryptographic code, today run by Chrome for most HTTPS connections; and Ur/Web, a production-quality domain-specific language for Web applications.