Bhagyaraja Adapa
Introduction
Introduction
- First year PhD student
- Research Interest : Hardware Security
- Advisor: Prof. JV Rajendran
- Department of Electrical and Computer Engineering
- Texas A&M University
Publications
Publications
- Bhardwaj Swati, Shashank Raghuraman, Bhagyaraja Adapa, and Amit Acharyya. "Vector Cross Product and Coordinate Rotation Based nD Hybrid FastICA." Journal of Low Power Electronics 14, no. 2 (2018): 351-364.
- Adapa Bhagyaraja, Dwaipayan Biswas, Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya, and Koushik Maharatna. "Coordinate Rotation-Based Low Complexity $ K $-Means Clustering Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 4 (2017): 1568-1572.
- Bhardwaj Swati, Adapa Bhagyaraja, R. Shashank, Pranit Jadhav, Dwaipayan Biswas, Amit Acharyya, and Ganesh R. Naik. "Low complexity single channel ICA architecture design methodology for pervasive healthcare applications." In Signal Processing Systems (SiPS), 2016 IEEE International Workshop on, pp. 39-44. IEEE, 2016.
- Bhardwaj Swati, Pranit Jadhav, Bhagyaraja Adapa, Amit Acharyya, and Ganesh R. Naik. "Online and automated reliable system design to remove blink and muscle artefact in EEG." In Engineering in Medicine and Biology Society (EMBC), 2015 37th Annual International Conference of the IEEE, pp. 6784-6787. IEEE, 2015.
- Vemishetty Naresh, Pranit Jadhav, Bhagyaraja Adapa, Amit Acharyya, Rajalakshmi Pachamuthu, and Ganesh R. Naik. "Affordable low complexity heart/brain monitoring methodology for remote health care." In Engineering in Medicine and Biology Society (EMBC), 2015 37th Annual International Conference of the IEEE, pp. 5082-5085. IEEE, 2015.
Contact details
Contact details
Email
Email
Lab
Lab
Room 111, Wisenbaker Engineering Research Center
188 Bizzell Street
College Station
Texas 77843
USA
LinkedIn
LinkedIn
https://www.linkedin.com/in/adapabhagyaraja
Google scholar
Google scholar
https://scholar.google.co.in/citations?user=a0yCzc0AAAAJ&hl=en
Projects
Projects
- Secure Hardware verification
- Design of the secure processor