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General information
General information
ID: DCE 08399
Course name: Digital systems (Sistemas digitais)
Department: Computing science and electronics
Undergraduate program: Computer engineering
Requirements: Digital circuits (Eletrônica digital)
Credits: 3
Hours (h): 60 (45T + 15L)
Semester: 2022-2
Lecture: Friday; 9h to 12h
Lab: Tuesday; 14h or 15h
Course topics
Course topics
Introduction to digital systems
Introduction to hardware description languages (HDL)
Combinational Logic Design
Sequential logic design and controllers blocks
Datapath components
Register-transfer level (RTL) design
Memory components and hierarchy
Physical Implementation with CIs and FPGAs
Programmable processors and microprogramming
Schedule (link)
Bibliography
Bibliography
Vahid, 2008; Vahid F, Sistemas digitais: projeto otimização e HDLs, Bookman, 2008 (lib. id.: 621.382:004 V127s)
eBook: Select the option "Plataforma Digital Minha Biblioteca" in "bibliotecas-digitais.ufes.br".
Floyd, 2007; Floyd T, Sistemas digitais: fundamentos e aplicações, 9 ed. Bookman, 2007 (lib. id.: : 621.32 F645s 9.ed.)
eBook: Select the option "Plataforma Digital Minha Biblioteca" in "bibliotecas-digitais.ufes.br".
Tocci, 2011; Tocci R, Sistemas digitais, princípios e aplicações, 11 ed. Prentice Hall, 2011 (lib. id.: : 621.382:004 T631s 11.ed.)
Chu, 2008; Chu P, FPGA prototyping by VHDL examples, Wiley, 2008 (lib. id.: : 621.382:004 C559f)
Wakerly, 2006; Wakerly J, Digital design: principles and practices, (link*), Prentice Hall, 2006 (lib. id.: : 621.382 W149d 4.ed.)
Hwang, 2006; Hwang E, Digital logic and microprocessor design with VHDL (link*), Thomson, 2006 (lib. id.: : 621.382:004 H991d)
Damore, 2005; DamoDamore R, VHDL - Descrição e síntese de circuitos digitais (link*), LTC, 2005 (lib. id.: : 004.312.44 D164v)
Pedroni, 2010; Pedroni V, Eletrônica digital moderna e VHDL, Elsevier, 2010 (lib. id.: : 621.382:004 P372e)
Ordonez, 2006; Ordonez E et al, Microcontroladores e FPGAs: aplicações em automação, Novatec, 2006 (lib. id.: : 621.3.049.77 M843m)
Ashenden, 2000; Ashenden P, VHDL tutorial, Elsevier (link*)
*: link to online available resources
lib. id.: library identifier
Course activities
Course activities
- Combinational Logic Design
Contents:
Switches; The transistor; Boolean Logic Gates; Boolean Algebra; Representations of Boolean Functions; Combinational Logic Design Process; More Gates; Decoders and Muxes; (S3)
Combinational Logic Optimizations and Tradeoffs; Combinational Logic Description Using HDL
Pre-class activities:
Reading of Chapter 2 [1] and Section 6.2 [1]
Filling in a form with evaluation questions
Preparing of Speech and Sending of Slides
Class activities:
Speech Presentation and Discussion
Post-class activities:
Evaluating: Ex. 2.6; Ex 2.26; and Ex 2.33 [1]
2. Sequential Logic Design: Controllers
2. Sequential Logic Design: Controllers
Contents:
Storing One Bit; FSM; Controller Design; More on Flip-Flops and Controllers; (S3)
Product Profile—Pacemaker (S1)
Sequential Logic Optimizations and Tradeoffs; Sequential Logic Description Using HDL
Pre-class activities:
Reading of Chapter 3 [1] and Section 6.3 [1]
Filling in a form with evaluation questions
Preparing of Speech and Sending of Slides
Class activities:
Speech presentation and Discussion
Post-class activities:
Evaluating Examples 3.2; Ex 3.7-3.12 [1].
3. Datapath Components
3. Datapath Components
Contents:
Registers; Adders; Comparators; Multiplier; Subtractors; ALU; Shifters; Counters and Timers (S3)
Product Profile: An Ultrasound Machine (S1)
Register Files; Datapath Component Tradeoffs; Datapath Component Description Using HDL
Pre-class activities:
Reading of Chapter 4 [1]
Filling in a form with evaluation questions
Preparing of Speech and Sending of Slides
Class activities:
Speech presentation and Discussion
Post-class activities:
Simulating of Examples 4.3-4.4; 4.6-4.8; 4.11; 4.12; Ex. 4.18-4.20; 4.23; 4.25 [1]
4. RTL design
4. RTL design
Contents:
High-Level State Machines; RTL Design Process; More RTL Design; Determining Clock Frequency; Behavioral-Level Design: C to Gates; (S3)
Memory Components: Queues; Hierarchy—A Key Design Concept; (S3)
Product Profile: Cell Phone (S1)
RTL Design Optimizations and Tradeoffs; RTL Design Using HDL
Pre-class activities:
Reading of Chapter 5 [1]
Filling in a form with evaluation questions
Preparing of Speech and Sending of Slides
Class activities:
Speech presentation and Discussion
Post-class activities:
Simulating of Examples 5.1-5.7; 5.11; 5.12 [1]
5. Physical Implementation on ICs
5. Physical Implementation on ICs
Contents:
Manufactured IC Types; Off-the-Shelf Programmable IC; Other Off-the-Shelf IC Types; Trends, and Comparison
Product Profile: Giant LED-Based Video Display with FPGAs (S1)
Pre-class activities:
Reading of Chapter 7 [1]
Filling in a form with evaluation questions
Preparing of Speech and Sending of Slides
Class activities:
Speech presentation and Discussion
6. Programmable Processors
6. Programmable Processors
Contents:
Basic Architecture; A Three-Instruction Programmable Processor; A Six-Instruction Programmable Processor; Example Assembly and Machine Programs; Further Extensions to the Programmable (S14)
Pre-class activities:
Reading of Chapter 8 [1]
Filling in a form with evaluation questions
Preparing of Speech and Sending of Slides
Class activities:
Speech presentation and Discussion
Laboratory activities
Laboratory activities
Combinational circuits using the Basic kit
Introduction to the Quartus II software
Sequential circuits using the Kit with programable IC
Introduction to hardware description languages
Projects using the Board with programable IC
Stepper motor driver project (S4)
Keypad encoder project (S4)
Digital clock project (S3)
Timer project (S3)
Microwave oven project (S14)
Relevant information
Relevant information
University schedule 2022 (link)
External resources
External resources
Installation of Quartus II (yt)
Google Sites
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