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General information
General information
Course name: Digital systems (Sistemas digitais)
Undergraduate school: Computer engineering
Requirements: Digital circuits (Eletrônica digital)
Credits: 4
Hours per semester (h): 60
Lecture (h): 45
Laboratory (h): 15
Schedule information
Schedule information
Introduction to digital systems
Introduction to hardware description languages (HDL)
Combinational Logic Design.
Sequential logic design and controllers blocks
Datapath components
Register-transfer level (RTL) design
Memory components and hierarchy
Physical Implementation with CIs and FPGAs
Programmable processors and microprogramming
Bibliography
Bibliography
Vahid, 2008; Vahid F, Sistemas digitais: projeto otimização e HDLs, Bookman, 2008 (library identifier: 621.382:004 V127s)
Floyd 2007; Floyd T, Sistemas digitais: fundamentos e aplicações, 9 ed. Bookman, 2007 (li: 621.32 F645s 9.ed.)
Chu, 2008; Chu P, FPGA prototyping by VHDL examples, Wiley, 2008 (li: 621.382:004 C559f)
Tocci, 2011; Tocci R, Sistemas digitais, princípios e aplicações, 11 ed. Prentice Hall, 2011 (li: 621.382:004 T631s 11.ed.)
Wakerly, 2006; Wakerly J, Digital design: principles and practices, (link*), Prentice Hall, 2006 (li: 621.382 W149d 4.ed.)
Wakerly, 2000; Wakerly J, Digital design: principles and practices, 3 ed, Prentice Hall, 2000
Hwang, 2006; Hwang E, Digital logic and microprocessor design with VHDL (link*), Thomson, 2006 (li: 621.382:004 H991d)
Damore, 2005; DamoDamore R, VHDL - Descrição e síntese de circuitos digitais (link*), LTC, 2005 (li: 004.312.44 D164v)
Pedroni, 2010; Pedroni V, Eletrônica digital moderna e VHDL, Elsevier, 2010 (li: 621.382:004 P372e)
Ordonez, 2006; Ordonez E et al, Microcontroladores e FPGAs: aplicações em automação, Novatec, 2006 (li: 621.3.049.77 M843m)
Ashenden, 2000; Ashenden P, VHDL tutorial, Elsevier (link*)
*: link to online available resources
Semester 2019-1
Semester 2019-1
Tuesday: 08:40 (2h) at room LPD of wing 3
Thursday: 08:40 (2h) at room 02 of wing 3
Schedule in detail (link)
Moodle platform - AVA (link)
First quiz: May 7nd
Second quiz: July 9nd
Final exam: July 16th
First part
First part
Contents
Contents
Introduction to digital systems and its implementation
Introduction to HDL
Combinational Logic Design
Combinational Logic Design and HDL
Sequential logic design and controllers blocks
Sequential logic design and controllers blocks and HDL
Datapath components (or Operational blocks)
Datapath components and HDL
Readings
Readings
Sections 1.1-1.3 and B.1-B.4 of Book 1 (Vahid, 2008)
Sections 9.1 of Book 1
Sections 2.1-2.10 and 2.13 of Book 1
Sections 9.2 of Book 1
Sections 3.1-3.5, 3.8, 3.9 of Book 1 (Vahid, 2008)
Section 9.3 of Book 1 (optionally Sections 4.1-4.4 of Book 3)
Sections 4.1-4.10, 4.13, 4.14 of Book 1 (Vahid, 2008)
Section 9.4 of Book 1
Exercises
Exercises
Exercises 1.27-1.33 and 3-5 of Section B.5 of Book 1
(Optionally Sections 1.1-1.4 of Book 3)
Exercises 2.53-2.59 of Book 1
(Optionally exercises 9.1-9.11)
Exercises 3.23-3.45, 3.46 of Book 1 (Vahid, 2008)
(Optionally exercises 9.12-9.15 of Book 1)
Exercises 4.3-4.6, 4.10-4.20, 4.25-4.40, 4.43-4.45, 4.56-4.62 of Book 1
(Optionally exercises 9.16-9.29 of Book 1)
Second part
Second part
Contents
Contents
Register-transfer level (RTL) design
RTL design and HDL
Optimization in RTL design
Components of memory and classification
Hierarchy
Physical Implementation with CIs and FPGAs
Programmable processors and microprogramming
Synthesis of low complexity hardware
Readings
Readings
Sections 5.1-5.5, 5.11, 5.12 of Book 1
Section 9.4 of Book 1
Sections 6.1, 6.5 of Book 1
Sections 5.6, 5.7 of Book 1 (Optionally Sections 10.1-10.8 of Book 2)
Section 5.8 of Book 1
Sections 7.1-7.7 of Book 1 (Optionally Sections 11.1-11.8 of Book 2)
Sections 8.1-8.7 of Book 1 (Optionally Sections 12.1-12.8 of Book 2)
(Optionally Chapters 5- of Book 3)
Exercises
Exercises
Exercises 5.2-5.13, 5.24-5.28 of Book 1
(Optionally 9.30-9.35 of Book 1)
Exercises 6.32, 6.33 of Book 1
Exercises 5.36-5.48 of Book 1 (Vahid, 2008)
Exercises 5.47-5.56 of Book 1
Exercises 7.20-7.31, 7.37, 7.38 of Book 1 (Vahid, 2008)
Exercises 8.1-8.22 of Book 1 (Vahid, 2008)
Lab
Lab
Scripts
Scripts
Digital clock (pdf)
Shift registers (pdf)
Memory and storage (pdf)
Programmable logic devices (i)
Programmable logic devices (ii)
ALU (pdf)
Gate level combinational circuits (pdf)
Quartus
Quartus
Manual (link) and instructions for downloading (link)
ISE
ISE
Manual (link) and Manual Nexys2 (link)
Video-clips showing how to implement, simulate and download projects using ISE and Nexys2 kit
Video-clips showing how to import projects using ISE and Nexys2 kit
Relevant readings
Relevant readings
Peligrini C, Claude Elwood Shannon e A Symbolic of Relay and Switching Circuits: tornando um computador uma máquina semiótica, Revista de comunicação e cultura, v7, n1, 2006 (pdf)
Additional information (in Portuguese)
Additional information (in Portuguese)
Calendário acadêmico 2018 da universidade (pdf)
Dispositivos lógicos programáveis (link)
Dispositivos lógicos programáveis (link)
VHDL SD2 (link)
Nexys 2 manual (link)
DSP and VHDL (link) - code availble
FPGA and DSP Laboratory (link) - code availble
Course on FPGA Design and VHDL (link) - slides available
Intel FPGA solutions (link)
Xilinx development zone (link)
Additional resources
Additional resources
Google Sites
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