Abstract: DNNs largely overwhelm conventional computing systems because the latter is severely bottlenecked by the data movement between processing units and memory. As a result, novel and intelligent computing systems become inevitable. In this talk, I will be focusing on the emerging ferroelectric (FeFET) technology and its great potential in building efficient in-memory computing architectures. I will present unprecedented dual-port FeFET which is completely disturbance free demonstrating its ability to offer scaling down the FE layer thickness down to merely 3nm while it can still store 8 states (i.e., 3-bit MLC-FeFET). Further, I will also explain how abstracted reliability models can be developed from device physics to circuits and later employed at the system and algorithm levels towards realizing HW/SW codesign for robust in-memory computing. I will discuss how FeFET-based in-memory computing outstandingly synergizes with Binarized Neural Networks (BNNs) and brain-inspired Hyperdimensional Computing (HDC) in which reliable machine learning can be realized on unreliable emerging FeFET technologies.

Abstract: Performing ever-demanding AI tasks directly on the resource-constrained edge devices calls for unprecedented energy-efficiency of edge AI hardware. AI hardware today consumes most energy through data movement between separate compute and memory units. Compute-in-memory (CIM) architectures using Resistive RAM (RRAM) overcome this challenge by storing weights in dense analog RRAM array and performing computation directly within memory. However, the energy-efficiency benefit of CIM usually comes at the cost of functional flexibility and computational accuracy, hampering its practical use for many edge applications that require processing multiple modalities of sensory data (e.g. image, audio). Such trade-offs between efficiency, versatility and accuracy cannot be addressed by isolated improvements on any single layer of the design.

In this talk, we present our attempts to ameliorate this fundamental trade-off through a full-stack co-optimization from device and circuit to architecture and algorithm. By integrating multiple innovations including a voltage-mode sensing scheme, a transposable neurosynaptic array architecture, and non-ideality-aware model training and fine-tuning techniques, we demonstrated NeuRRAM, a RRAM CIM chip that simultaneously delivers a high degree of reconfigurability for diverse model architectures, state-of-the-art energy-efficiency, and software-comparable inference accuracy measured across various AI benchmarks including image classification, speech recognition, and image recovery.

Abstract: As Moore’s law is approaching to the end, designing specialized

hardware accelerator along with the software that map the applications

onto the specialized hardware is a promising solution.

The hardware design determines the peak performance, while the

software is also important as it determines the actual performance.

Hardware/software (HW/SW) co-design can optimize the hardware

acceleration and software mapping in concert and improve

overall performance. However, the current flow designs hardware

and software in isolation. More importantly, both hardware and

software are difficult to design and optimize due to the low level

programming and huge design space. In this talk, we will introduce

AHS, an Agile framework for Hardware specialization and Software

mapping for AI applications. AHS can automatically partition the

hardware and software space, generate the hardware accelerator,

and map the software onto it synergistically.

Abstract: This talk first provides an introduction to quantum computing, then proceeds to give an application of quantum machine learning towards drug discovery.

Abstract: As the complexity of modern hardware systems explode, fast and effective design space explorations for better IC (Integrated Circuits) implementations become more and more difficult to achieve due to higher demands of computational resources. Recent years have seen increasing use of decision intelligence in IC design flows to navigate the design solution space in a more systematic and intelligent manner. To address these problems, IBM Research has been working on the AI/ML-infused IC design orchestration project in order 1) to enable the IC design environment on Hybrid Cloud platform so that we can easily scale up/down the workloads according to the computation demands, and 2) to produce higher Quality-of-Results (QoRs) in shorter total Turn-Around-Time (TAT). In this talk, I will describe how we provide a scalable IC design workload execution that produces higher performance designs by utilizing AI/ML-driven automatic parameter tuning capability. We first see how we can build a cloud-based IC design environment including the containerized digital design flow on Kubernetes clusters. Then, we extend the containerized design flow with the automatic parameter tuning capability using AI/ML techniques. Finally, we demonstrate that the automatic parameter tuning can be executed in more scalable and distributable manners using the Ray platform. I will use the actual design environment setups, the code snippets, and results from the product IC designs as evidence that the proposed method can produce higher quality of IC designs using the automatic parameter tuning methodologies.