Speakers

Accelerating Deep Neural Networks with Analog Nonvolatile Memory Devices

Abstract: Deep Neural Networks (DNNs) are very large artificial neural networks trained using very large datasets, typically using the supervised learning technique known as backpropagation. Currently, CPUs and GPUs are used for these computations. Over the next few years, we can expect special-purpose hardware accelerators based on conventional digital-design techniques to optimize the GPU framework for these DNN computations.

Even after the improved computational performance and efficiency that is expected from these special-purpose digital accelerators, there would still be an opportunity for even higher performance and even better energy-efficiency for inference and training of DNNs, by using neuromorphic computation based on analog memory devices.

In this presentation, I discuss the origin of this opportunity as well as the challenges inherent in delivering on it. While I will briefly discuss materials and devices for analog volatile and non-volatile memory, and circuit and architecture choices and challenges, I will focus on challenges in computer-aided design as well as the current status and prospects.

Design Space Exploration for In-Memory Computing with Associative Memories

Abstract: In-memory computing, where certain data processing is performed directly in the memory array, can be an effective accelerator architecture for data-intensive applications. Associative memory (AM), a type of memory that can efficiently “associate” an input query with appropriate data words/locations in the memory, is a powerful in-memory computing core. Nonetheless, harnessing the benefits of AM requires extensive cross-layer design space exploration spanning from devices and circuits to architectures and systems. In this talk, I will use several representative AM accelerator designs to show the vast design space involved. In particular, I will highlight how different non-volatile memory technologies can be exploited to implement various types of AM for some popular machine learning applications. I will introduce a circuit/architecture evaluation tool, Eva-CAM, that supports design space exploration of AM based IMC accelerators.

Generation, Execution and Model Optimized Stochastic Computing Based Inference Acceleration

Abstract: Stochastic computing (SC) has seen a renaissance in recent years as a means for machine learning acceleration due to its compact arithmetic and approximation properties. Still, SC accuracy remains an issue, with prior works either not fully utilizing the computational density or suffering from significant accuracy losses. In this talk, I will discuss various optimizations we have developed over the past few years spanning generation of stochastic streams, effective pipelined architectures for SC execution and efficient training and neural architecture search for SC-based accelerators culminating in GEO or Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks. GEO bridges the accuracy gap between stochastic computing and fixed-point neural networks while delivering up to 5.6X higher throughput and 2.6X lower energy. I end with a brief discussion of the two silicon prototypes of GEO that we have taped out and measured, including one in-memory implementation.

The Interplay of Online and Offline Machine Learning for Industrial Design Flow Tuning

Abstract: Modern logic and physical synthesis tools provide numerous options and parameters that can drastically affect design quality; however, the large number of options leads to a complex design space difficult for human designers to navigate. Fortunately, machine learning approaches and cloud computing environments are well suited for tackling complex parameter tuning problems like those seen in VLSI design flows. This talk proposes a holistic approach where online and offline machine learning approaches work together for tuning industrial design flows. We describe a system called SynTunSys (STS) that has been used to optimize multiple industrial high-performance processors. STS consists of an online system that optimizes designs and generates data for a recommender system that performs offline training and recommendation. Experimental results show the collaboration between STS online and offline machine learning systems as well as insight from human designers provide best-of-breed results. Finally, we discuss potential new directions for research on design flow tuning.

CHIMERA: Efficient DNN Training and Inference at the Edge with On-Chip Resistive RAM

Abstract: Performing energy-efficient deep neural network training and inference at the edge is challenging with current memory technologies, and as neural networks grow in size and computation, this problem is getting worse. Emerging non-volatile memories may be the answer with resistive RAM (RRAM) being one of the most promising candidates. To evaluate RRAM in the context of neural network training and inference at the edge, we design, fabricate, and test CHIMERA, the first non-volatile edge AI SoC using foundry provided on-chip RRAM macros and no off-chip memory. CHIMERA achieves 0.92 TOPS peak performance and 2.2 TOPS/W. We scale inference to 6x larger DNNs by connecting 6 CHIMERAs with just 4% execution time and 5% energy costs, enabled by communication-sparse DNN mappings that exploit RRAM non-volatility through quick chip wakeup/shutdown. We demonstrate the first incremental edge AI training which overcomes RRAM write energy, speed, and endurance challenges. Our training achieves the same accuracy as traditional algorithms with up to 283x fewer RRAM weight update steps and 340x better energy-delay product. We thus demonstrate 10 years of 20 samples/minute incremental edge AI training on CHIMERA.

Integrated Circuit Design Redaction through Transistor-Level Programming (TRAP)

Abstract: As the majority of design houses follow the globalized fabless semiconductor manufacturing business model to curtail cost, their products are exposed to a range of security and trustworthiness threats, such as Intellectual Property (IP) theft, unauthorized over-production and counterfeiting. Therefore, the ability to hide sensitive or proprietary portions of a design from a potentially untrusted foundry is becoming paramount for IP protection. Design obfuscation solutions, such as logic locking, which embed the secret IP within broader functionality through the use of a secret key, offer a certain level of protection against brute-force attacks, yet have been shown vulnerable to intelligent attacks, such as the clever use of a Boolean Satisfiability (SAT) solver. To prevent an untrusted fab from obtaining sensitive IP, an alternative approach could rely, instead, on completely redacting parts of the design from the fabricated silicon and reinstating them through post-manufacturing programming. While this idea is, in itself, rather straightforward, realizing it in a cost-effective manner is quite challenging. Indeed, using embedded Field Programmable Gate Arrays (eFPGAs) to implement the omitted portion of the function provides high security levels but results in significant area, power and performance overhead. Towards alleviating this overhead, we developed a Transistor-Level Programmable (TRAP) fabric and an extensive framework for designing and implementing cost-effective hybrid ASIC/Programmable Integrated Circuits (ICs), wherein sensitive IP can be protected through design redaction. In this presentation, we will discuss the design of the latest version of our TRAP fabric in GlobalFoundries' 12nm technology, the CAD tool-flow necessary for supporting such hybrid designs ASIC/Programmable ICs, and the protection that TRAP-based design redaction offers against both brute-force and intelligent attacks seeking to recover the redacted IP. .