Journals
A. Das and N. A. Touba, "A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote" in Electronics, vol. 9, no. 5, article 709, May 2020.
A. Das and N. A. Touba, "A New Class of Single Burst Error Correcting Codes with Parallel Decoding" in IEEE Transactions on Computers, vol. 69, no. 2, pp. 253-259, Feb. 2020.
A. Das, A. Sanchez-Macian, F. Garcia-Herrero, N. A. Touba and J. A. Maestro, "Enhanced Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories" in IEEE Transactions on Nanotechnology, vol. 18, pp. 1023 - 1026, Oct. 2019.
A. Das and N. A. Touba, "Efficient One-Step Decodable Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories" in IEEE Transactions on Nanotechnology, vol. 18, pp. 575 - 583, May 2019.
Refereed Conferences
S. Dutta, S. C. R. Chinni, A. Das and N. A. Touba, "Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder", in Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1-6, 2023.
A. Das and N. A. Touba, "Selective Checksum based On-line Error Correction for RRAM based Matrix Operations", in Proc. of IEEE VLSI Test Symposium (VTS), paper RP3.3, 2020. PPT
A. Das and N. A. Touba, "Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory Systems" in Proc. of IEEE VLSI Test Symposium (VTS), paper 7A.2, 2019. PPT
A. Das and N. A. Touba, "A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation" in Proc. of IEEE VLSI Test Symposium (VTS), paper 1C.1, 2019. PPT
A. Das and N. A. Touba, "Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches" in Proc. of IEEE Latin American Test Symposium (LATS), pp. 1-6, 2019. PPT
A. Das and N. A. Touba, "Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMs", in Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1-6, 2018. (Received Best Paper Award) PPT
A. Das and N. A. Touba, "Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMs", in Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 219-224, 2018. PPT
A. Das and N. A. Touba, "Systematic b-adjacent symbol error correcting reed-solomon codes with parallel decoding", in Proc. of IEEE VLSI Test Symposium (VTS), paper 7A.1, 2018. PPT
A. Das and N. A. Touba, "Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel Cells", in Proc. of IEEE International Conference on Computer Design (ICCD), pp. 391-394, 2017. PPT
A. Das, S. Dash, B.C. Babu and A.K. Sahoo, "Design and implementation of FPGA based linear all digital phase-locked loop", in Proc. of Annual IEEE India Conference (INDICON), pp. 280-285, 2012.
A. Das, S. Dash, B.C. Babu and A.K. Sahoo, "A novel phase detection system for linear all-digital phase locked loop", in Proc. of IEEE Students Conference on Engineering and Systems (SCES), pp. 1-6, 2012.
Technical Reports
A. Das and A. Gerstlauer, "simCUDA: A C++ based CUDA Simulation Framework", CERC, UT Austin, Technical Report UT-CERC-16-01, May 2016.