Program

Hal Finkel (ASCR)

Hal is a program manager for computer-science research in the US Department of Energy Office of Science's Advanced Scientific Computing Research (ASCR) program. Prior to joining ASCR, Hal was the Lead for Compiler Technology and Programming Languages at Argonne’s Leadership Computing Facility. As part of DOE's Exascale Computing Project (ECP), Hal was a PathForward technical lead and PI/Co-PI of several multi-institution activities. Hal serves as vice chair of the C++ standards committee. He also helped develop the Hardware/Hybrid Accelerated Cosmology Code (HACC), a two-time IEEE/ACM Gordon Bell Prize finalist. Hal graduated from Yale University in 2011 with a Ph.D. in theoretical physics focusing on numerical simulation of early-universe cosmology.

Caleb Adams (NASA)

Caleb Adams works in the Robust Software Engineering group of the Intelligent Systems Division at NASA’s Ames Research Center. Caleb is currently developing software for the Distributed Spacecraft Autonomy experiment onboard the Starling mission and is a subtopic manager for Neuromorphic Computing. Prior to working at NASA Caleb co-founded the University of Georgia’s Small Satellite Research Lab, where he received a Master’s in Computer Science. He is interested in researching autonomous systems, computer vision, and high-performance edge computing.

Josiah Hester (NSF CNS Career awardee, Sloan Fellow)

Josiah Hester is the Breed Chair of Design and Assistant Professor of Computer Engineering at Northwestern University. He works in intermittent computing and battery-free embedded computing systems. He applies his work to health wearables, interactive devices, and large-scale sensing for sustainability and conservation, supported by multiple grants from the NSF, NIH, and DARPA. He was named a Sloan Fellow in Computer Science and won his NSF CAREER in 2022. He was named one of Popular Science’s Brilliant Ten, won the American Indian Science and Engineering Society Most Promising Scientist/Engineer Award and the 3M Non-tenured Faculty Award in 2021. His work has received four Best Paper type Awards and seven Best Presentation type Awards, and been featured in the Wall Street Journal, Scientific American, BBC, Popular Science, Communications of the ACM, the Guinness Book of World Records, among many others.

Deliang Fan (NSF SHF Career awardee)

Dr. Deliang Fan is an Assistant Professor in the School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA. He will be promoted to Associate Professor with tenure in the School of ECEE, ASU, officially starting from the Fall 2022 semester. He received his M.S. and Ph.D. degrees, under the supervision of Prof. Kaushik Roy, in Electrical and Computer Engineering from Purdue University, West Lafayette, IN, USA, in 2012 and 2015, respectively.

Dr. Fan’s primary research interest includes Energy Efficient and High Performance Processing-In-Memory Circuit, Architecture and Algorithm cross-layer software & hardware co-design, with applications in Deep Neural Network, Data Encryption, Graph Processing and Bioinformatics; Machine Learning System Hardware-Software Co-Design; Adversarial AI security; Brain-inspired (Neuromorphic) Computing. He has authored and co-authored 140+ peer-reviewed international journal/conference papers in above area. He is the receipt of NSF Career award, best paper award of 2019 ACM Great Lakes Symposium on VLSI, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), and 2017 IEEE ISVLSI. He is also the best IP paper award of 2022 DATE. His research paper was also nominated as best paper candidate of 2019 Asia and South Pacific Design Automation Conference (ASPDAC) and 2019 International Symposium on Quality Electronic Design (ISQED). He is also the technical area chair of DAC 2021, GLSVLSI 2019-2022, ISQED 2019-2022, and the financial chair of ISVLSI 2019. He served as technical reviewers for 30+ international journals/conferences, such as Nature Electronics, IEEE TNNLS, TVLSI, TCAD, TNANO, TC, TCAS, etc. He also served as the Technical Program Committee member of DAC, ICCAD, HPCA, MICRO, WACV, GLSVLSI, ISVLSI, ASP-DAC, etc. Please refer to https://dfan.engineering.asu.edu/ for more details.

Yanzhi Wang (ARMY YFA awardee)

Dr. Yanzhi Wang is currently an associate professor and faculty fellow at Dept. of ECE at Northeastern University, Boston, MA. He received the B.S. degree from Tsinghua University in 2009, and Ph.D. degree from University of Southern California in 2014. His research interests focus on model compression and platform-specific acceleration of deep learning applications. His work has been published broadly in top conference and journal venues (e.g., DAC, ICCAD, ASPLOS, ISCA, MICRO, HPCA, PLDI, ICS, PACT, ISSCC, AAAI, ICML, NeurIPS, CVPR, ICLR, IJCAI, ECCV, ICDM, ACM MM, FPGA, LCTES, CCS, VLDB, PACT, ICDCS, RTAS, Infocom, C-ACM, JSSC, TComputer, TCAS-I, TCAD, TCAS-I, JSAC, TNNLS, etc.), and has been cited above 11,000 times. He has received six Best Paper and Top Paper Awards, and one Communications of the ACM cover featured article. He has another 11 Best Paper Nominations and four Popular Paper Awards. He has received the U.S. Army Young Investigator Program Award (YIP), IEEE TC-SDM Early Career Award, Massachusetts Acorn Innovation Award, Martin Essigmann Excellence in Teaching Award, Massachusetts Acorn Innovation Award, Ming Hsieh Scholar Award, and other research awards from Google, MathWorks, etc. He has received 22 federal grants from NSF, DARPA, IARPA, ARO, ARFL/AFOSR, etc.. He has participated in a total of $40M funds with personal share $8M. Five of his former Ph.D./postdoc students become tenure track faculty at Univ. of Connecticut, Clemson University, Chongqing University, Texas A&M University, Corpse Christi, and Cleveland State University.

Helen Li (Duke University)

Hai “Helen” Li is Clare Boothe Luce Professor and Acting Chair of the Electrical and Computer Engineering Department at Duke University. Her current research focuses on neuromorphic computing systems, deep-learning acceleration and security, memory design and architecture, and high-performance and energy-efficient computing systems. She is a Fellow of ACM and IEEE.

Iris Bahar (Colorado School of Mines )

Since January 2022, Iris Bahar is the Department Head and Professor at the Colorado School of Mines. Her research interests lie broadly in the areas of computer system design and design automation. A main theme of her research over the years has been energy-efficient and reliable computing, from robots, to high-end processors, embedded systems, and emerging technologies.

Between her M.S. and Ph.D studies, she worked for 5 years at Digital Equipment Corporation, mainly on their VAX microprocessor designs. Prior to joining CS@Mines as Department Head, she was faculty at Brown University for 26 years with a joint appointment in the School of Engineering and Department of Computer Science.

Her research has been continuously funded since 1997 through various industrial and government sources, including the NSF (including a career award), DARPA, DoD, the Semiconductor Research Corporation (SRC), Intel, IBM, Facebook, and NASA. She is the 2019 recipient of the Marie R. Pistilli Women in Engineering Achievement Award and the Brown University School of Engineering Award for Excellence in Teaching in Engineering. She is an IEEE Fellow an ACM Distinguished Scientist.

Sharon Hu (University of Notre Dame)

X. Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame, USA. Her research interests include low-power system design, circuit and architecture design with emerging technologies, real-time embedded systems and hardware-software co-design. She has published more than 400 papers in these areas. Some of her recognitions include the Best Paper Award from the Design Automation Conference and the International Symposium on Low Power Electronics and Design, and NSF Career award. She has participated in several large industry and government sponsored center-level projects and was a theme lead in an NSF/SRC E2CDA project. She served as the General Chair and TPC Chair of Design Automation Conference, Real-Time Systems Symposium, etc. She is the Editor-in-Chief of ACM Transactions on Design Automation of Electronic Systems, and has also served as Associate Editor for a number of ACM and IEEE journals. X. Sharon Hu is a Fellow of the ACM and a Fellow of the IEEE.

Robert Wille (Technical University of Munich)

Robert Wille is a Full and Distinguished Professor at the Technical University of Munich, Germany, and Chief Scientific Officer at the Software Competence Center Hagenberg, Austria. He received the Diploma and Dr.-Ing. degrees in Computer Science from the University of Bremen, Germany, in 2006 and 2009, respectively. Since then, he worked at the University of Bremen, the German Research Center for Artificial Intelligence (DFKI), the University of Applied Science of Bremen, the University of Potsdam, and the Technical University Dresden. From 2015 until 2022, he was Full Professor at the Johannes Kepler University Linz, Austria, until he moved to Munich. His research interests are in the design of circuits and systems for both conventional and emerging technologies. In these areas, he published more than 350 papers and served in editorial boards as well as program committees of numerous journals/conferences such as TCAD, ASP-DAC, DAC, DATE, and ICCAD. For his research, he was awarded, e.g., with Best Paper Awards, e.g., at TCAD and ICCAD, an ERC Consolidator Grant, a Distinguished and a Lighthouse Professor appointment, a Google Research Award, and more.

Shobha Vasudevan(Google Brain Research)

Shobha Vasudevan is a research scientist in Google Research, involved in strategy, roadmap, research and productization of AI/ML for systems. Between 2019-2022, she was a research scientist in the Brain team. Prior to joining Google, Shobha was a tenured professor at the ECE and CS departments at the University of Illinois at Urbana-Champaign. Shobha is a recipient of NSF Career award, ACM SIGDA Outstanding faculty award, IEEE Early Career Award, UIUC Deanś award for excellence in research, IBM faculty awards, Google faculty awards and several best paper awards. She serves on several IEEE boards for standards, technical program committees and ACM/IEEE journal editorial boards. She volunteers with local school districts for developing K-5 STEM modules.

Siddhartha Nath (Nvidia Research)

Siddhartha (Sid) Nath is currently a Sr. Research Scientist at NVIDIA Corp. His research interests include improving digital implementation runtime and PPA metrics using advanced machine learning techniques and EDA optimization. Prior to NVIDIA, Sid worked at Synopsys Inc. where he lead several ML in EDA optimization efforts and deployed successful products. His work on pre-route delay optimization was the first ML-driven product to be used for tapeout by top semiconductor companies at 7nm and below nodes. Sid earned his Ph.D in Computer Science and Engineering from UC San Diego and has over 30 publications at top EDA/VLSI conferences and journals, best paper nomination and best paper award at ISPD. He also holds five granted US patents as well as several more in the pipeline.

Subhendu Roy (Cadence)

Subhendu Roy received the B.E. degree in electronics and telecommunication engineering from Jadavpur University, Kolkata, India, in 2006, the M.Tech. degree in electronic systems

from the Indian Institute of Technology Bombay, Mumbai, India, in 2009, and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin, Austin, TX, USA, in 2015. He is currently a software architect in the Machine Learning group in Cadence Design Systems, San Jose. He has 10 years of industry experience in several EDA companies, namely, a start-up company Atrenta which was acquired by Synopsys, Intel Programmable Solution Group along with internship experience in IBM T. J. Watson Research Center and Mentor Graphics. He has worked in varied areas of EDA, such as clock tree synthesis, adder synthesis, power and timing optimization, gate-sizing, reliability and machine learning guided datapath optimization and design space exploration. He has served as reviewer in many journals/conferences, including TVLSI, TCAS-I and II, TCAD, TODAES, DAC, GLSVLSI, ISLPED etc. Dr. Roy was a recipient of the Best Paper Award at ISPD’14.

Elizabeth Iwasawa (Leidos)

Elizabeth Iwasawa is the Quantum Technology Lead of the Leidos Innovation Center (LInC), the ground-breaking research and development heart of Leidos (formerly SAIC). She is currently shaping Leidos’ quantum strategy and research portfolio, focusing on key development areas in quantum communications, sensing, simulations, and computing. Her other focus is fostering cross-development of Leidos employees with a wide variety of technical backgrounds to leverage a truly multi-disciplinary, collaborative, and industry-applicable approach to quantum research.

Elizabeth started her physics career on a dare her senior year of college by taking a Quantum Mechanics class just before graduating with a degree in creative writing. Her newly discovered passion saw her take on a M.S. in Materials Science followed by a Ph.D. in Particle Astrophysics from Drexel University. She worked with the IceCube South Pole Neutrino Observatory and Super Cryogenic Dark Matter Search (CDMS) collaborations before turning to industry. Prior to joining Leidos, she supported sub-surface maritime autonomy research and was a member of the Quantum Technology Council at BAE Systems.