Prof. (Dr.) Pankaj P Prajapati

• Ph.D in EC Engineering (VLSI)

• M.E. in  EC (VLSI) Engineering 

• B.E. in EC Engineering

• Working as an Associate Professor in Vishwakarma Government Engineering College, Chandkheda since 24/04/2025.

• Worked as an Assistant  Professor in L D Engineering College, Ahmedabad from 17/06/2011 To 23/04/2025.

• Worked as a HOD in EC department of S.S.P.C at Visnagar from 01/08/2009 to 16/6/2011. 

•  Worked as a lecturer in EC department of S.S.P.C at Visnagar from 15/6/05 to 31/7/09.

• Worked as an adhoc lecturer in EC department of Govt. Polytechnic at Porbandar from 16/1/02 to 19/4/05.

1. VLSI Design

2. Embedded System

1. Basic Electronics

2.  Analog & Digital Electronics 

3. Data Communication & Networking

4. VLSI

5. Testing and Verification

6. Embedded System

7.  Microprocessor and controller

[1]  Pankaj P. Prajapati and Mihir V. Shah, “Two stage CMOS operational amplifier design using particle swarm optimization algorithm,” in Proceeding of IEEE UP Section              Conference on Electrical, Computer and Electronics, IIIT- Allahabad, Dec. 2015, DOI: 10.1109/UPCON.2015. 7456700.

[2]  Pankaj P. Prajapati, Swati A. Sharma, and Mihir V. Shah, “Design of  CMOS operational amplifier using differential evolutionary algorithm,” in NCCICT-2016, GEC, 

      Gandhinagar, ISBN 978-93-5288-056-0, pp. 108-111, Sep. 2016.

[3]  Pankaj P. Prajapati and Mihir V. Shah, “Automated sizing methodology for CMOS Miller operational transconductance amplifier,” in Soft Computing: Theories and 

      Applications, Advances in Intelligent Systems and Computing, Springer, Singapore, ISSN No. 2194-5357, vol. 584, pp. 301-308, Nov. 2017, 

         DOI.org/10.1007/978-981-10-    5699-4_29.

[4]  Pankaj P. Prajapati and Mihir V. Shah, “Performance estimation of differential evolution, particle swarm optimization, and cuckoo search algorithms,” in International    

     Journal of Intelligent Systems and Applications (IJISA), ISSN No. 2074-9058, vol. 10, no. 6, pp. 59-67, June 2018, DOI: 10.5815/ijisa.2018.06.07.

[5]  Pankaj P. Prajapati and Mihir V. Shah, “Optimization of CMOS current mirror load-based differential amplifier using hybrid cuckoo search and particle swarm optimization         algorithm,” in Journal of Artifical Intelligence Research & Advances, eISSN No. 2395-6720, vol. 5, no. 3, pp. 71-78, Feb. 2019.

[6]  Pankaj P. Prajapati, Krunal P. Acharya, and Mihir V. Shah, “Optimization of CMOS Miller OTA using differential evolutionary algorithm,” in International Journal of Intelligent       Systems and Applications in Engineering, ISSN No. 2147-6799, vol. 7, no. 1, pp. 47-51, March 2019, DOI: https://doi.org/10.18201/ijisae.2019151254.

[7] Pankaj P. Prajapati, Krunal P. Acharya, and Mihir V. Shah,  “Optimal cell sizing of CMOS two-stage operational amplifier using cuckoo search algorithm,” in Journal  of 

     Artificial Intelligence Research and Advances, eISSN No. 2395-6720, vol. 6, no. 2, pp. 109-118, July 2019. 

[8]  Pankaj P. Prajapati and Mihir V. Shah, “Automatic circuit design of CMOS Miller OTA using cuckoo search algorithm,” in International Journal of Applied Metaheuristic      

      Computing (IJAMC), DOI: 10.4018/IJAMC.2020010103, ISSN No. 1947-8283, vol. 11, issue 1, pp. 36-44,  Jan 2020.   

[9]  Pankaj P. Prajapati and Mihir V. Shah, “Automatic sizing of CMOS based analog circuits using cuckoo search algorithm,” in International Journal of Intelligent Systems     

      Technologies and Applications, ISSN No. 1740-8865, Jan 2020.

[10]  Divyesh R. Keraliya, Balvant Makwana, Pankaj P. Prajapati  “Optimization  of Detection Error Rate in Cooperative Sensing using ACO algorithm” in  ADBU               

        Journal of Engineering Technology(AJET),  ISSN No. 2348-7305, Volume 10, Issue 4, Dec. 2021

[11]  Kirit V. Patel, Mihir V. Shah, Pankaj P. Prajapati, Anil J. Kshatriya,  “Design and  Implementation of Effective Elliptic Curve Cryptography    Accelerator using              

        Hardware/Software Co-Design on Zynq Board”,   International Journal of Engineering Trends and Technology, Volume 70,  Issue 8, pp.327-335, August  2022.

[12]  Pankaj P. Prajapati, Anilkumar J. Kshatriya, Sureshbhai L. Bharvad, Abhay B. Upadhyay, "Performance analysis of CMOS based analog circuit design  with PVR 

        variation”, Bulletin of Electrical Engineering and Informatics, Feb 2023. DOI: 10.11591/eei.v12i1.4357 

[13] Sureshbhai L. Bharvad, Pankaj P. Prajapati and Anilkumar J. Kshatriya”  Meta  Heuristic Optimization Approach For CMOS Based Analog Circuit  Design And    

       Performance Evaluation of Evolutionary Algorithms, ICTACT   Journal on Soft  Computing ISSN: 2229-6956 (online), Volume: 13, Issue: 02, January 2023. 

[14] Pankaj P. Prajapati, A. J. Kshatriya, D. N. Patel, S. K. Gonsai, H. B. Tank, and K. R. Sheth, “Comparative analysis of meta heuristics algorithm for differential amplifier        

       design,” Bull. Electr. Eng. Inform., vol. 12, no. 6, pp. 3395–3401, Dec. 2023, doi: 0.11591/eei.v12i6.6153 

[15] Pankaj P. Prajapati, A. J. Kshatriya, A. M. Patel, G. Sah, C. Dave, K. R. Sheth, N. Patel, and K. V. Patel, "Sizing of dual-stage operational amplifiers through PVT-aware   

       circuit optimization in 0.18 μm CMOS technology," Int. J. Intell. Syst. Appl. Eng., vol. 12, no. 4, pp. 1148–1155, July 2024. https://www.ijisae.org/index.php/IJISAE/article/view/6360 

[16]  Mihir Panchal, Pankaj P. Prajapati, FPA-DQN: A Fairness-and Pressure-Aware Dueling Deep Q-Network for Adaptive Traffic Signal Control Using UAV-               Based Trajectory Data, Indian Journal of Science and Technology, July 2025, vol. 18, no.28, 2257-2272,  DOI: 10.17485/IJST/v18i28.73

[17]  Pankaj P. Prajapati, Rahul Maru, Kinjal R Seth, Alpesh M. Patel, Anil J. Kshatriya, Nitin J. Bathani, Kirit V. Patel  "Implementation of Teaching Learning                 Based Optimization (TLBO) Algorithm to optimize CMOS based Analog Circuits" IJST (Web of Science indexed Journal ),  Vol.18, No. 34, pp 2784-2793,              Sep. 2025 DOI: 10.17485/IJST/v18i34.1373 

[18]   Pankaj P. Prajapati, Patel AM, Kshatriya AJ, Patel KV, Sah G, Dave C, Sheth KR, Patel DH. (2025) Design Optimization of CMOS Folded-Cascode OTAs           via Multi-Objective Evolutionary Algorithms: PSO, DE, and CSPSO Approaches. Indian Journal of Science and Technology. 18(36):2942-2952. Oct. 2025             https://doi.org/10.17485/IJST/v18i36.1552 

• Method and System for Computer Aided CMOS Based Analog Circuit Design, Indian Patent office ,Published, May 2025 

• IETE, ISTE