• Ph.D in EC Engineering 

• M.E. in  EC Engineering 

• B.E. in EC Engineering

• Working as an Associate Professor at Vishwakarma Government Engineering College, Chandkheda since 24/04/2025.

• Worked as Associate Professor at L. D. Engineering College, Ahmedabad from 19/05/2011 To 23/04/2025.

1. Image Processing

2. AI/ML

3. Satellite Communication

1. Satellite Communication

2. Network Theory

3. Control Theory

4. Fiber Optic Communication 

5. Digital Signal Processing

6. Machine Learning

[1]  Kinjal R Sheth “Transfer Learning Based Fine-Tuned Novel Approach for Detecting Facial Retouching,” Iraqi J. Electr. Electron. Eng., vol. 20, no. 1, pp. 84–94, Jun.              2024, doi: 10.37917/ijeee.20.1.9.

[2]  Kinjal R Sheth and Vishal S Vora “Preserving authenticity: transfer learning methods for detecting and verifying facial image manipulation,” Vietnam J. Sci. Technol.,             vol. 62, no. 3, pp. 562–576, Jun. 2024, doi: 10.15625/2525-2518/18626.

[3]  Kinjal R Sheth , Vishal S Vora. 2023. “A Comparative Study on Image Forgery-Facial Retouching.” 12(2):851–59. doi: 10.11591/eei.v12i2.4481. 

[4]   Kinjal R Sheth  2024. “An Intelligent Approach to Detect Facial Retouching Using Fine Tuned VGG16.” International Journal of Biometrics 1(1):1–11. doi:        

       10.1504/ijbm.2024.10062315. 

[5]  Pankaj P. Prajapati, Rahul Maru, Kinjal R Seth, Alpesh M. Patel, Anil J. Kshatriya, Nitin J. Bathani, Kirit V. Patel  "Implementation of Teaching Learning             Based Optimization (TLBO) Algorithm to optimize CMOS based Analog Circuits" IJST (Web of Science indexed Journal ),  Vol.18, No. 34, pp 2784-2793,          Sep. 2025 DOI: 10.17485/IJST/v18i34.1373 

     [6]  Pankaj P. Prajapati, A. J. Kshatriya, A. M. Patel, G. Sah, C. Dave, Kinjal R Sheth,  N. Patel, and K. V. Patel, "Sizing of dual-stage operational amplifiers through PVT-  

            aware circuit optimization in 0.18 μm CMOS technology," Int. J. Intell. Syst. Appl. Eng., vol. 12, no. 4, pp. 1148–1155, July 2024  

            https://www.ijisae.org/index.php/IJISAE/article/view/6360 

     [7]  Sima K Gonsai, Kinjal Ravi Sheth, Dhavalkumar N. Patel, Hardik B. Tank, Hitesh L. Desai, Shilpa K. Rana, and Suresh L Bharvad. 2024. “Exploring the                     

            Synergy: AI and ML in Very Large Scale Integration Design and Manufacturing.” Bulletin of Electrical Engineering and Informatics 13(6):3993–4001. 

            doi: 10.11591/eei.v13i6.8594. 

    [8]  Pankaj P. Prajapati, A. J. Kshatriya, D. N. Patel, S. K. Gonsai, H. B. Tank, and K. R. Sheth, “Comparative analysis of meta heuristics algorithm for differential amplifier                design,” Bull. Electr. Eng. Inform., vol. 12, no. 6, pp. 3395–3401, Dec. 2023, doi: 0.11591/eei.v12i6.6153 

   [9]  Pankaj P. Prajapati, Patel AM, Kshatriya AJ, Patel KV, Sah G, Dave C, Sheth KR, Patel DH. (2025) Design Optimization of CMOS Folded-Cascode OTAs             via Multi-Objective Evolutionary Algorithms: PSO, DE, and CSPSO Approaches. Indian Journal of Science and Technology. 18(36):2942-2952. Oct. 2025             https://doi.org/10.17485/IJST/v18i36.1552 

1. Lifetime membership of ISTE