JAYESH NAVNITLAL DIWAN

Ph.D. (Pursuing) in Digital VLSI Design.

M.Tech in VLSI Design from Nirma University. 

B.E. in Electronics and Communication Engineering from Vishwakarma Government Engineering College.

Worked as Assistant Professor at Indus University for 7 Years

Worked as Telecom Officer at BSNL for 1 Year.

Worked as Lecturer at LDRP Institute of Technology and Research for 1 Year.

Digital VLSI Design

VLSI Signal Processing

Asynchronous Designs

VLSI Design

VLSI Signal Processing

Testing and Verification

VLSI Test Principles and Architecture

Wavelet Transform Analysis

Digital VLSI Design

Analog Circuit Design

Basic Electronics 

Digital Signal Processing

Journal Publication: " Novel Design Approach of 64-bit Full Adder with Sky130 PDK using Open-Source VLSI Tools", International Journal of Engineering Research in Electronics and Communication Engineering (IJERECE), ISSN (Online) 2394-6849, Volume 11 Issue 09 September 2024

Journal Publication: "Design and Characterization of a Novel FinFET based NCL Cell Library for High Performance Asynchronous Circuits", International Journal of Electrical and Electronics Research (IJEER) Scopus indexed Journal, VOLUME 11 ISSUE 1 Feb 2023, ISSN: 2347-470X / https://doi.org/10.37391/IJEER.110111

 Journal Publication: "A Novel NCL Threshold Gate Implementation for Low Power Asynchronous Designs using FinFETs", International Journal of Engineering Trends and Technology, IJETT Scopus indexed Journal, VOLUME 70 ISSUE 5, May 2022, ISSN: 2231-5381/ https://doi.org/10.14445/22315381/IJETT-V70I5P232

 Conference Publication: "Design And Throughput Analysis Of 4 Bit Asynchronous Pipelined Multiplier Using Null Convention Logic", 2021 IEEE 2nd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC), 26-28 Nov. 2021, DOI: 10.1109/AESPC52704.2021.9708509, Publisher: IEEE, Electronic ISBN:978-1-6654-4299-2

 Journal Publication: "DRONE BASED IMAGING SYSTEM FOR WASTE ASSESSMENT", Multidisciplinary International Research Journal of Gujarat Technological University, VOLUME 4 ISSUE 1 JANUARY 2022, ISSN: 2581-8880

Journal Publication: "REVIEW OF LOW POWER LFSR DESIGN TECHNIQUES", Multidisciplinary International Research Journal of Gujarat Technological University, VOLUME 3 ISSUE 1 JANUARY 2021, Online ISSN: 2581-8880

Journal Publication: "Optimization 8-bit ALU using Hybrid LUT/MUX FPGA Design using VerilogHDL", International Journal for Technological Research in Engineering (IJTRE), Volume 5, Issue 8 April 2018, ISSN: 2347-4718

Journal Publication: "Review of NCL Based Design", International Journal for Technological Research in Engineering (IJTRE), Volume 5, Issue 8 April 2018, ISSN: 2347-4718