Highly-Digitized RF Receivers Based on RF Sigma-Delta ADCs
Highly-Digitized RF Receivers Based on RF Sigma-Delta ADCs
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Abstract
In the 1990’s, during the expansion of wireless communications, several architectures were proposed to
realize fully integrated CMOS RF receivers. Since the 2000’s and until today the dominant architectures
to realize these receivers are: Zero-IF and Low-IF. Using these architectures, it is possible to realize very
compact and power efficient receivers for specific wireless communication standards operating at any
fixed RF center frequency. Recently, with the multiplication of the number of wireless communication standards, there has been a strong need to integrate the RF receivers of several wireless communication standards into the same chip. Low-power Zero-IF and Low-IF architectures are usually designed to satisfy the specifications of a
single wireless communication standard operating at a specific center frequency. In order to satisfy the
demand for multi-standard receivers two main architectures have been proposed. The first multi-standard architecture simply consists in having multiple Zero-IF or Low-IF receivers on the
same chip. This architecture is very power efficient but it has led to a significant increase in chip area and
cost. Furthermore, it requires a complex power management system to selectively activate each receiver
based on the desired standard. The second multi-standard architecture is mainly based on a single
receiver having tunable and reconfigurable RF/analog blocks capable of adapting to different
specifications and center frequencies. Making RF/analog blocks tunable and reconfigurable introduces
significant complexity, which substantially increases the power consumption of this second architecture
compared to conventional single-standard designs.
This tutorial explores the realization of a multi-standard receiver using a highly-digitized architecture. In
this case, the RF signal is directly converted to the digital domain using an RF Analog-to-Digital Converter
(ADC). The digital RF signal is then down-converted and filtered in the easily programmable digital
domain. In this architecture, the most challenging block is the RF ADC which needs to sample RF signals
at several gigahertz. In this tutorial, we will focus on a specific type of RF ADCs: bandpass Sigma-Delta
ADC. This type of ADC is particularly adapted to RF applications since it is capable of directly converting a
narrow-band signal centered around an RF frequency. Highly-digitized RF receivers based on RF bandpass
Sigma-Delta ADCs achieve a high-level of flexibility and reconfigurability with a low power consumption.
In this tutorial, we will present the design and implementations of several RF bandpass Sigma-Delta ADCs
having different orders. Measurement results from fabricated circuits realized in 130nm and 65nm
technologies will be presented, analyzed and compared to the state of the art.
Prof. Hassan Aboushady, Ph.D., HDR, IEEE,
Received the B.Sc. degree in Electrical Engineering from Cairo University, Egypt, in 1993, the M.Sc. and Ph.D. degrees in Electrical Engineering and Computer Science from Sorbonne University, Paris, France, in 1996 and 2002 respectively. He also obtained his accreditation to supervise research (HDR) from the same University in 2010. Hassan Aboushady is currently an Associate Professor at Sorbonne University, Campus Pierre and Marie Curie, Paris, France. He worked on the design of high resolution audio Digital-to-Analog converters at Philips Research Laboratories (currently NXP), Eindhoven, The Netherlands. He also worked on the implementation of a baseband continuous-time Sigma-Delta modulator for RF receivers at STMicroelectronics, Crolles, France. Hassan Aboushady was a visiting professor for several months at the French University in Egypt, UFE, the Federal University of Rio Grande do Norte, UFRN, Brazil, and "Technologico de Monterrey", ITESM, Guadalajara, Mexico, in 2007, 2011 and 2013 respectively. During the academic year 2012-2013, he was on a sabbatical leave at the Ecole Polytechnique, LIPCM laboratory, working on the design of analog circuits using organic electronics. His research interests include Sigma-Delta modulation, Analog/RF circuit design, Analog-to-Digital and Digital-to-Analog conversion, security in Analog and mixed-signal circuits as well as AI hardware accelerators. He is the author and co-author of more than 100 publications in these areas. He is the recipient of the 2004 best paper award in the IEEE Design Automation and Test in Europe Conference, as well as the recipient and the co-recipient of the 2nd and the 3rd best student paper awards of the IEEE Midwest Symposium on Circuits and Systems in 2000 and 2003 respectively. Dr. Aboushady is Senior IEEE member, an IEEE-CAS distingushed lecturer and a member of the IEEE Circuits and Systems for Communications Committee (CASCOM). He also served as an Associate Editor of the IEEE Transactions on Circuits & Systems II.
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