FPGA versus GPU for Speed-Limit-Sign Recognition(ITSC 2018, Nov. 4-7, 2018, Hawaii)

Optimizing separable convolution using CUDA and TVM (UCD Modern Parallel Computing EEC 289Q)

GPU performance evaluation for ray-tracing using OpenGL (UCD Graphics Architecture EEC 277)

Real-time Vehicle detection and localization on Android using OpenCV (UCD Embedded EEC 284)

Other projects:

• Utilize Nvidia TensorRT and CUDA to optimize various CNN models and deploy on GPUs (Xmotors internship)
• GTSDB - German Traffic Sign Benchmarks detection using CNN models on GPU and FPGA
• Robot-car in Verilog (NCU Graduation Project): Implemented a wireless Robot-car in Verilog on Altera board for emergency rescue mission with sound and thermal detection.
• 16-bit MIPS processor design and Implementation in Verilog (NCU Computer Architecture course).
• EDA macro placement in C++ (NCU Data Structure course): Completed a routability-driven macro placement (Problem D: 2015 CAD contest at ICCAD)
• Bullet Blocking game in Verilog (NCU Digital System Design course): Implemented a bullet blocking game in Verilog and synthesized it into FPGA with LED 7-segment display, keyboard, DIP Switch, LCM, and buttons.
• PostgreSQL Project (UCD Database ECS165A): Processed data from incomplete input files in CVS format and then performed queries using PostgreSQL and Python.