The variety of hardware used in modern supercomputers challenges software teams to provide performant solutions across a diverse set of programming interfaces. Using a supercomputer for both simulation and analysis—both as a post-process and as an “in situ” process executing concurrently with a simulation—is becoming increasingly common. To facilitate adoption and promote usage, an international working group has formed to develop a standard interface for analytical rendering across hardware and vendor platforms. As rendering interfaces become easier to use across the supercomputing landscape, it also becomes easier to use certain hardware-optimized functionality, such as vector mathematics and spatial sorting structures, directly within scientific simulations to model phenomena such as radiative transfer and to compute behavior such as particle advection. Hardware-optimized ray tracing engines, tuned by processor manufacturer engineers, can accelerate simulation critical sections that depend on ray-based traversals and intersections. This workshop will serve as a venue for developers and users of simulations, visual analysis codes, and analytic rendering to present early results in this growing cross-discipline field. This meeting will continue the conversation toward standardization of analytic interfaces to facilitate their expanding role throughout scientific workflows, including data evaluation, insight formulation, discovery communication, and presentation-quality artifact generation.

This workshop will publish short-format technical papers aimed at sharing early results in the application of analytic rendering and in the integration of hardware-optimized analysis libraries into simulation codes. The aim is to build awareness and develop community for analytic rendering capabilities and best practices for both post-processing and “in situ” analyses. The workshop also will advance the use of hardware-optimized analytic rendering libraries, such as ray tracing engines, in simulation codes that make extensive use of spatial sorting structures (e.g., k-nearest neighbor) and ray-like vector calculations (e.g., Monte Carlo radiative transfer, particle advection). Using hardware-tuned methods for traversal and intersection in the inner loops of such simulations can provide significant performance enhancement, particularly on next-generation GPU hardware with dedicated ray processing logic. Hardware-tuned ray tracers, however, have not yet been widely adopted due to the graphics-centric nature of their interfaces and terminology. This workshop seeks to build a community among simulation users and developers, visualization developers, and hardware-optimized analysis library developers in order to standardize interfaces for simulation and for coprocessing of simulation and analysis.

Relevance and Impact to SC Community: Use of analytic rendering on supercomputers continues to grow as remote machines are used for the entire scientific discovery cycle, from original data generation through final analysis for publication. The use of hardware-optimized ray-tracers in scientific simulation represents an untapped opportunity for performance improvement, particularly for current and near-future machines with accelerated ray-tracing hardware. This workshop aims to represent a diverse set of experiences and viewpoints across HPC and serve as an interchange among simulation, analysis, and hardware communities to grow common capabilities and cross-pollinate innovations among the member communities. Through this workshop, the SC Community will gain insights to improve performance for both simulation and analytic workflow components. We also hope this workshop will inspire additional exploration of cross-discipline code exchange to improve the rate of scientific discovery.

Workshop Format and Planned Schedule: The half-day workshop will primarily be presentation of early work in the application of analytic rendering and use of hardware-accelerated rendering libraries for simulation. We will invite a keynote speaker to give an extended presentation on relevant topics and to further encourage attendance. If we have sufficient papers worthy of acceptance, we will shorten the keynote presentation.

· 0:00 – 1:00 hour – paper presentations (three papers, 15 min + 5 min questions each)

· 1:00 – 1:30 hour – SC workshop break

· 1:30 – 2:30 hour – IEEE CiSE SE presentations (four papers, 10 min + 5 min questions each)

· 2:30 – 3:30 hour – paper presentations (three papers, 15 min + 5 min questions each)

Organizers

Paul Navrátil Texas Advanced Computing Center

Estelle Dirand TOTAL

Pascal Grosset Los Alamos National Laboratory

Christiaan Gribble SURVICE Engineering