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DAY 1: Tuesday, 25 November 2025
Prof. Yuan Du, Nanjing University
Title : Exploration of General-Purpose Photonic-Electronic Computing Chips and Systems
Time : 2:40 p.m. - 3:10 p.m.
Synopsis of talk
This report explores the development of general-purpose photonic-electronic integrated computing chips and systems, aiming to overcome the limitations of traditional electronic computing in speed and power efficiency. By leveraging the high bandwidth and low latency of photonics, combined with mature electronic processing, such hybrid architectures offer promising solutions for next-generation computing. The design challenges and methodologies for key electronic chiplets in AI-focused optoelectronic computing systems are discussed, particularly how to balance the inherent inaccuracies of photonic computing with the precision needs of AI applications.
Biography
Yuan Du received his B.S. degree from Southeast University (SEU), Nanjing, China, and his M.S. and Ph.D. both from University of California, Los Angeles (UCLA). He worked for Kneron Inc., San Diego, CA, USA from 2016 to 2019, as a leading hardware architect. Since 2019, he has been with Nanjing University, Nanjing, China, as an Associate Professor. His current research interests include designs of high-speed interconnect transceivers, machine-learning hardware accelerators and opto-electronic integrated circuits and systems.
Prof. Jian Zhao, Shanghai Jiao Tong University
Title : Energy-Efficient and Environmentally Resilient Transceivers for Body Channel Communication
Time : 3:10 p.m. - 3:40 p.m.
Synopsis of talk
Body-Channel Communication (BCC) has emerged as a promising interconnect technology in Wireless Body-Area Networks (WBANs), offering advantages such as low transmission loss and enhanced physical security. This tutorial provides a comprehensive overview of BCC transceivers (TRXs), beginning with the fundamental principles of BCC and channel modeling techniques. It then delves into design methodologies for highly energy-efficient and environmentally robust TRX circuits, covering both narrowband and wideband implementations. Additionally, measurement techniques and future research directions will be explored. This tutorial aims to equip designers of wearable healthcare SoCs and other low-power WBAN devices with practical insights and technical expertise.
Biography
Jian Zhao (S’14, M’17, SM’21) received his Ph.D. degree from the School of Mechanical Engineering, Nanjing University of Science and Technology, China, in 2017. He served as a visiting scholar in the VLSI and Signal Processing Lab at the National University of Singapore from 2012 to 2015. From 2017 to 2019, he joined the Department of Electronic Engineering, Tsinghua University, as a postdoctoral researcher. He is currently a Tenured Associate Professor in the School of Integrated Circuits, Shanghai Jiao Tong University, China. His research interests include biomedical and bio-inspired circuits and systems. He has authored and co-authored over 80 technical papers and 2 book chapters. He is the recipient of the IEEE BioCAS 20th Anniversary Top WiCAS/YP Contributor Award, the ISCAS 2024 Best Demonstration Award, and the ICTA 2021 Best Paper Award. He is currently an Associate Editor for the IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), and SPJ Cyborg and Bionic Systems. He has also served as an Associate Editor for the IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) and received the TCAS-I Best Associate Editor Award in 2021. He is a member of the Digital Communication Standing Committee of CASS and the Co-founder/Past-Chair of the IEEE Shanghai Section Young Professional Affinity Group.
DAY 2: Wednesday, 26 November 2025
Louis Chee, ASEM
Title : Introduction About ASEM
Time : 9:45 a.m. - 10:30 a.m.
Synopsis of talk
Introduces ASEM (Advanced Semiconductor Academy of Malaysia)—a national initiative dedicated to shaping Malaysia’s future talent pipeline in semiconductors. The talk explores how ASEM connects universities, industry partners, and global technology leaders to empower youth with real-world, industry-driven skills.
Attendees will gain insights into ASEM’s mission, including its flagship programs such as the NSEP, GSEP talent pathways, Malaysia Semiconductor Recruitment Day (MSRD), Nationwide Recruitment Roadshow, and industry-integrated semiconductor seminars & workshops.
This sharing will also talk about how ASEM is building a sustainable ecosystem for talent development—from hands-on technical training to industry placements and international collaboration.
Biography
Louis Chee, currently serve at ASEM, where I contribute to building Malaysia’s next-generation talent pipeline in Semiconductor and AI. This role strengthens my ability to bridge industry, education, and investment — creating opportunities that support both business growth and national talent development.
Prior to this, i worked as an experienced professional in the equity crowdfunding (ECF) industry, I bring a strong blend of fundraising strategy, financial insight, and project execution to every campaign I lead. With over 35 successful campaigns closed and RM35 million raised, I have a proven track record in helping businesses secure the capital they need through compelling pitches, structured investor engagement, and disciplined campaign management.
My expertise spans ECF regulations, market trends, investor behaviour, and platform best practices. I specialise in developing tailored fundraising strategies, managing cross-functional stakeholders, and communicating clearly with entrepreneurs, investors, and partners. I am equally strong in project management — from planning and budgeting to risk management and timely delivery.
Prof. Kun-Chih Chen,
National Yang Ming Chiao Tung University
Title : From Heat to Heart: Cerebral Intelligence in NoC-AI Design and Applications
Time : 10:30 a.m. - 11:00 a.m.
Synopsis of talk
Artificial Intelligence (AI) has achieved remarkable success across domains such as image recognition, speech processing, and industrial automation, yet the growing model complexity and data scale have introduced significant challenges in power efficiency, adaptability, and thermal reliability for AI accelerators. This talk presents a holistic exploration of thermal-aware Network-on-Chip (NoC)-based AI system design, spanning from algorithmic innovation to practical application. It begins with smart thermal management for multi-core systems, featuring compressive-sensing-based sensor placement and adaptive machine-learning-driven proactive thermal control. The discussion then moves to sustainable and flexible AI architectures, including Taiwan’s first NoC-based reconfigurable DNN accelerator and reliability-enhancing computing techniques such as stochastic and block spiking neural networks. Finally, lightweight neural architecture search and transfer-learning-based anomaly detection are applied to smart manufacturing for efficient remaining useful life prediction, illustrating how these innovations collectively enable energy-efficient, reliable, and sustainable AI computing from heat to heart.
Biography
Kun-Chih (Jimmy) Chen is currently an Electric Junior Chair Professor at National Yang Ming Chiao Tung University (NYCU), Taiwan. His research interests include Multiprocessor SoC (MPSoC) design, Neural network learning algorithm design, Reliable system design, VLSI/CAD design, and Smart manufacturing. Prof. Chen heads many services in IEEE Circuits and Systems Society, such as IEEE JETCAS Guest Editor, General Chair of NoCArc 2020. Prof. Chen has received several prestigious national and international awards, including the Ta-You Wu Memorial Award of NSTC (i.e., Early Career Award in Taiwan), Chinese Institute of Electrical Engineering (CIEE) Outstanding Youth Electrical Engineer Award, Taiwan IC Design Society Outstanding Young Scholar Award, IEEE Tainan Section Best Young Professional Member Award, etc. Under his leadership, his research team became the first in Taiwan to win the IEEE ISCAS Best Student Paper Award and IEEE TVLSI Best Paper Award. He is an IEEE senior member.
Prof. Li Du, Nanjing University
Title : RAC-NAF: A Reconfigurable Analog Circuitry for Nonlinear Activation Function Computation in Computing-in-Memory
Time : 11:00 a.m. - 11:30 a.m.
Synopsis of talk
The emerging computing-in-memory (CIM) architecture minimizes data movement for efficient deep neural network (DNN) processing. However, CIM's energy efficiency is limited by its inability to process the massive nonlinear activation functions (AFs) in the analog domain. Current solutions require digital co-processors, forcing frequent, power-hungry analog-to-digital and digital-to-analog (AD/DA) conversions.
To address this, we propose RAC-NAF, a reconfigurable analog circuit that computes AFs using Taylor approximation and a segmentation method for accuracy. This pure analog approach eliminates AD/DA conversions for AFs. Experiments show RAC-NAF reduces AD/DA energy by up to 12.31×, improves total system energy efficiency by 2.34×–5.20×, with under 1% accuracy loss on various CIM accelerators.
Biography
Li Du (Senior Member, IEEE) received the B.S. degree from Southeast University, Nanjing, China, and the Ph.D. degree in electrical engineering from the University of California, Los Angeles (UCLA), USA. He is currently the Professor with the Department of Integrated Circuits, Nanjing University, China. His research interests include analog sensing circuit design, in-memory computing, and high-performance AI processors for edge sensing.
Dr. Yueting Li, Beihang University
Title : An Antiferromagnetic MRAM-Based Processing-in-memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks
Time : 11:30 a.m. - 12:00 p.m.
Synopsis of talk
Quantized convolutional neural network (QCNN) is an attractive approach that reduces hardware overheads, especially for energy-constrained systems. However, existing QCNNs still require nontrivial hardware resources and memory capacity in order not to compromise model accuracy. To address this issue, we propose an antiferromagnetic magnetic random-access memory (ARAM) based processing in memory (PIM) system, leveraging bit-level sparsity. Three optimization techniques are proposed to optimize hardware resource utilization while preserving CNN accuracy. First, the ARAM-based memory subsystem allows dynamic adaptation of variable bit-width across CNN layers. Second, the bit-level accelerator employs the bit-fusion format engineered for processing data from the ARAM subsystem. Third, a customized data path within the RISC-V core guarantees efficient instruction processing to the ARAM-based memory subsystem and bit-level accelerator, enabling optimal bit-level data transmission and computation. Experimental results demonstrate that this design remarkably reduces data movement by 50%–83% across existing CNNs. Compared to state-of-the-art designs, it enhances throughput and latency by an average of 5× and 10× , respectively. In addition, this design achieves speedups between 1.63× and 2.96× , outstripping other designs in AlexNet, VGG16, and ResNet18 benchmarks.
Biography
Yueting Li received her Ph.D. degree from Beihang University in 2024. Currently, she is a senior engineer and serving as a postdoc researcher in the Beihang University. Her research interests primarily focus on system integration, MRAM applications, near-memory computing systems, and neural network accelerator design. She serves as a reviewer for ACM/IEEE ICCAD, ACM/IEEE ASP-DAC, IEEE ISICAS, IEEE JETCAS, IEEE ICCC. She also serves as IEEE AICAS Local Chair, IEEE ISICAS Local Chair, IEEE CASS Summer School co-Chair and IEEE ICCC Section Chair. She has received the Best Demonstration Award at ACM/SIGDA University Design Demo, the Best Presentation Award at IEEE ICCC, and Finalist in the ISLPED Design Contest.
Dr Philippe Royannez, Maxlinear Singapore
Title : AI assisted Digital IC Design: Evolution or Revolution?
Time : 3:30 p.m. - 4:00 p.m.
Synopsis of talk
As AI Tools such as Chat-GPT and Claude, powered by very advanced LLMs, are now capable to generate code in various programming languages, what quality and practicality can we expect for HDL such as Verilog and VHDL and how much assistance can we expect for System on Chip design? In this presentation we will cover both design and verification aspects, starting from high level descriptions and specifications. We will deep dive into more specific requirements such as power, area, testability and code coverage. We will follow a pragmatic approach and present various examples and several contexts where AI can be of very high added value. We will also highlight weaknesses and potential improvements and we will try to quantify the productivity gain we can expect. Finally we will conclude with perspective and reflection on future developments for next AI tools generations.
Biography
Dr. Royannez is Senior Director of VLSI Design for Maxlinear Singapore. He has more than 3 decades of international Career in US, France, Germany, Finland and Singapore, where he worked at Siemens, Infineon, Texas Instruments, ST-Ericsson and Intel. He also managed RnD teams in Singapore, France, Beijing and Bangalore. He has specialized in all aspects of System-on-Chip Design and holds several patents on Ultra-Low Power digital design.
He is an IEEE Senior member and holds a Ph.D. in Electrical Engineering and Computer Science from Université Pierre et Marie Curie
Prof. Kain Lu Low, Xi'an Jiaotong-Liverpool University
Title : AI-Enhanced and Physics-Guided Framework for Accelerated Device Development and Design-Technology Co-Optimization
Time : 4:00 p.m. - 4:30 p.m.
Synopsis of talk
As semiconductor technologies enter the era of advanced nodes, the complexity of materials, device architectures, and design interactions continues to increase. Traditional TCAD-driven design–technology co-optimization (DTCO), while accurate, is limited by slow turnaround time and the need for expert-intensive tuning. This talk introduces an AI-enhanced and physics-guided methodology that accelerates device and circuit exploration while preserving physical interpretability. The first part highlights examples where physics-based TCAD is combined with machine learning and multi-objective optimization to identify promising design regions for emerging transistors, including steep-slope concepts and carbon-nanotube FETs. A unified graph-attention-based surrogate model further enables fast prediction of device behavior within DTCO flows. The second part presents AgenticTCAD, a multi-agent framework that uses domain-specific language models to automatically generate TCAD input files, run simulations, analyze results, and refine device parameters from natural-language descriptions. Together, these developments demonstrate a pathway toward intelligent, explainable, and scalable DTCO for future semiconductor technologies.
Biography
Kain Lu Low is an Associate Professor of Electrical & Electronic Engineering at Xi’an Jiaotong-Liverpool University. His work bridges device physics and AI to advance physics-guided, data-driven DTCO, TCAD surrogate modeling, and multi-agent LLM workflows for automated device design and optimization. Recent efforts include device-to-circuit co-optimization, steep-slope transistor exploration validated by DFT-NEGF, graph-attention TCAD surrogates for rapid DTCO, and agentic-AI framework for end-to-end TCAD code generation and device optimization. He earned a Ph.D. from the National University of Singapore and B.S./M.S. degrees from Purdue University. Previously, he worked at GlobalFoundries (Singapore) in design enablement and at Legend Design Technology (California) in circuit-simulator development. He serves as Vice Chair of the IEEE CASS-EDS Suzhou Joint Chapter.
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