GitHub repo: https://github.com/zfazal10/CPE487
Final Project page can be find in navigation menu on top right.
[2020-12-15] Got FPGA connected to VGA monitor on a 800x600 display. Completed Final project of 2 player Tic Tac Toe. Updated GitHub repository.
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[2020-12-10] Looked through code that Kristin put together. The logic made sense but only Kevin could be sure it worked since he had the board. Did research into getting graphics to work.
Contributions: FPGA Tutorial 4. VGA in VHDL on Altera DE1 Board, https://www.youtube.com/watch?v=WK5FT5RD1sU
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[2020-12-3] Typed out and planned the complete strategy that an unbeatable Tic Tac Toe AI would employ in single player mode. Later in the week the group decided that it would be best to keep the game to 2 player to keep it more reasonable and achievable. Completed Lab 6.
Contributions: FPGA Xilinx VHDL Video Tutorial, https://www.youtube.com/watch?v=Ob7B6x5g6tw
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[2020-11-24] Group started working on Tic Tac Toe. We found some useful resources online, while also trying to plan out the logic we would use for the game. Completed Lab 5.
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[2020-11-19] Completed Lab 4. Did a little research into Tic Tac Toe game.
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[2020-11-12] Our group of eight people realized we were too big so we split up into 2 groups. My group was me, Kevin, Kristin, and Stephen. Our project idea was to make a Tic Tac Toe game. Completed Lab 3.
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[2020-11-5] Completed Lab 2, formed group for final project
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[2020-10-29] Continued working on Lab 2. Went over remaining Labs in class.
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[2020-10-22] Went over Labs 2 and 3 in class, completed Lab 1.
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[2020-10-15] Started FPGA Lab 1, no class on Monday.
Contributions: How to Create a Finite-State MAchine in VHDL, https://www.youtube.com/watch?v=E-qEnSp1aCk
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[2020-10-8] Reviewed chapters 11: Data Objects, 12: Looping Constructs, and 13: Standard Digital Circuits in VHDL. Went over how to download and use Vivado software.
Contribution: Getting Started with Vivado, https://reference.digilentinc.com/vivado/getting_started/2018.2?_ga=2.268500529.1171230711.1606986829-185599489.1599582232
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[2020-10-01] Reviewed chapters 9: Structural Modeling in VHDL and 10: Registers and Register Transfer Level. Also continued to look at student websites and contributions. Identified group leaders.
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[2020-09-24] Reviewed chapter 8: Finite State Machine Design Using VHDL. Looked at VHDL code for 4-to-1 multiplexer and 1-to-4 demultiplexer. Formed group to share FPGA. Reviewed student websites to gain understanding of website requirements.
Contribution: How To Design A Finite State Machine, https://www.cs.princeton.edu/courses/archive/spr06/cos116/FSM_Tutorial.pdf
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[2020-09-17] Reviewed chapters 5, 6, and 7 in the textbook which were respectively about standard models, operators, and using VHDL for sequential circuits. We also started forming groups to share the FPGA's.
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[2020-09-10] Reviewed chapters 3 and 4 of textbook, which talked about entities and architecture as well as signal assignments. Also read the Node is Nonsense and installed GHDL.
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[2020-09-03] Reviewed the syllabus, created a Google site with a link to a GitHub repository, and studied the IEEE writing style