This part definitely had a bit of a learning curve, mostly getting the Vivado environment setup for our needs. This included getting the proper board files for the A7 board and ensuring that the constraints file was linked. Being as this was a starter project to get us used to VHDL code and flashing the code to the FPGA, it was really interesting to see the process of transforming the signals to binary then to a digital display on the board.
This part came easier than part A due to familiarity with the Vivado ecosystem. Rather than displaying a semi-static output, the hex counter program continuously looped counting up by "1" from 0000 to FFFF. Each new hex value the display would update to reflect the new value. This program was insightful to show how VHDL can still be sequential even though it is a concurrent language.