Digital Systems Design

GitHub

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Weekly Reports

[2020-09-01]

Reviewed Syllabus. Created this site and the GitHub repository.

[2020-09-03]

Covered chapters 1 and 2 of textbook. Installed Xilinx Vivado on my Windows 10 machine.

[2020-09-08]

Covered chapter 3 of textbook. Installed GHDL and GTKWave. Explored IEEE papers by Samuel K.Moore titled 'The Node is Nonsense' and 'A Better Way to Measure Progress in Semiconductors'.

[2020-09-10]

Covered chapter 4 of textbook. Ran the 'Hello, World' and 'Half Adder' VHDL programs using GHDL and GTKWave. The desired output was achieved for both (console output and GTKWave signal graph).

[2020-09-15]

Covered chapter 5 in textbook. Introduced processes, where statements are executed sequentially. Processes as a whole can be concurrent with other processes. Ran the 'Full Adder' VHDL program.

[2020-09-17]

Covered chapters 6 and 7 of textbook. Summarized VHDL operators. Explored D flip-flop and T flip-flop circuits which function like 'latches' on my pc.

[2020-09-22]

Covered chapter 8 of textbook. Explored the concept of 'finite-state machines.' Found the following YouTube video which demonstrates implementing a traffic-light system using a finite-state machine with VHDL - Lesson 92 - Example 62: Traffic Light Controller

[2020-09-24]

Reviewed chapter 8 of textbook and finite-state machines again. Covered GitHub's 'readme.md' file which allows for management of one's GitHub repository and how it displays on webpages.

[2020-09-29]

Covered chapter 9 of textbook. Introduced the concept of modular design using components. This technique promotes code reusability. Also touched on use of generics which allows the user to abstract their designs in terms of various parameters. The example in the text is a parity check routine that takes an N-sized binary array and returns 1 if the array represents an even number, and 0 if odd.

[2020-10-01]

Covered chapter 10 of textbook. Introduced RTL (Register Transfer Level) Design. RTL is commonly associated with 'data-path' design. When operating under these design principles, we are concerned with the transfer of data between registers, and the necessary timing involved.

[2020-10-06]

Covered chapter 11 of textbook. Summarized data object types including signals, variables, and constants. Covered declarations for each as well as their corresponding assignment operators. Users may define their own custom data types. Examined examples utilizing various data types.

[2020-10-08]

Finished textbook. Chapter 12 provided detail on useful looping constructs and various keywords. Chapter 13 provided a list of example processes. I typed up each example on my PC and I wrote the rest of the required code to run the example procedures (including the test benches) up to example 4 so far. I also contributed a batch script that takes the name of a VHDL file and automatically compiles it along with its corresponding test bench file and runs it in GTKWave (see run.bat on the GitHub repository).

[2020-10-16]

In class we were given a demonstration on settings up a Vivado project for Lab 1. Afterwards I attempted to repeat the steps with my lab group. However, I was unable to run the synthesis because of license issues. I have since created a new Xilinx account and am working on a fresh install with a brand new set of licenses.

[2020-10-20]

After successfully reinstalling Vivado and valid licenses, I managed to run the synthesis, run the implementation, and generate the bitstream file for both labs 1 and 2 (projects available on GitHut repository). However, I am waiting until a later date to write to the board, when I am able meet up with my team member, James Parisi, who is holding onto our FPGA, the Nexys A7-100T.

[2020-10-22]

Worked through lab 3. Ran synthesis, implementation, and generated bitstream. Inserted modifications for ball.vhd which changed the color and shape of the moving object displayed on the VGA signal. Still holding off to write to board memory.

[2020-10-27 - 2020-10-29]

Implemented the remaining labs (4, 5, and 6) in Vivado, including the required modifications. All memory configuration files are now ready to be uploaded onto the board, pending meetup with group members. Skimmed through the manual for the Nexys A7 100T to prepare for using the board.

[2020-11-03 - 2020-11-05]

Decided to write a research paper titled 'Storage and Memory Technologies and their Applications in FPGAs' for my final project. So far I've found a paper which compares performance between various memory architectures on FPGAs with many-core CPUs. It offers plenty of insight on the advantages and disadvantages of CPU cache, SRAM, and DRAM.

Additionally, I found this tutorial on using Vivado to simulate VHDL code. It demonstrates that Vivado actually offers the same functionality as GHDL in conjunction with GTKWave. For example, with a test bench file, Vivado can generate a waveform graph displaying the input and output signals over time, similar to GTKWave.

[2020-11-10]

I've continued researching for my paper and I created a publicly viewable Google doc containing the sources I am planning to use. They include lots of information on storage and memory technologies such as HDDs, NVMe SSDs, DRAM, Caching techniques, and NVRAM.

[2020-11-12]

Met up with James Parisi to write the project files to the Nexys A7-100T. Successfully completed labs 1 through 6. See lab images at this bottom of this page.

[11-17-2020 - 11-19-2020]

Initial draft of research paper is in relatively good shape. I've changed the working title to 'State of Storage and Memory Technologies'. The latest version of the draft can be found here.

[12-01-2020 - 12-03-2020]

Final version of research paper is complete. It is available in pdf format here.